Публікація: General Testing Models of SOC Hardware Software Components
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Дата
2008
Назва журналу
ISSN журналу
Назва тома
Видавництво
KNURE
Анотація
Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.
Опис
Ключові слова
Infrastructure Intellectual Property, Register Transfer Graph, System-on-a-Chip, Testing
Бібліографічний опис
Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96.