Open Electronic Archive of Kharkov National University of Radio Electronics
ISSN 2310-8061
Please use this identifier to cite or link to this item:
http://openarchive.nure.ua/handle/document/1954| Title: | General Testing Models of SOC Hardware Software Components |
| Authors: | Hahanov, V. Litvinova, E. Gharibi, W. |
| Keywords: | Infrastructure Intellectual Property Register Transfer Graph System-on-a-Chip Testing |
| Issue Date: | 2008 |
| Publisher: | KNURE |
| Citation: | Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96. |
| Abstract: | Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown. |
| URI: | http://openarchive.nure.ua/handle/document/1954 |
| Appears in Collections: | Кафедра автоматизації проектування обчислювальної техніки (АПОТ) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Хаханов_РИ_2008_1ENGLISH.pdf | 1.08 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.