Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1954
Title: General Testing Models of SOC Hardware Software Components
Authors: Hahanov, V.
Litvinova, E.
Gharibi, W.
Keywords: Infrastructure Intellectual Property
Register Transfer Graph
System-on-a-Chip
Testing
Issue Date: 2008
Publisher: KNURE
Citation: Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96.
Abstract: Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.
URI: http://openarchive.nure.ua/handle/document/1954
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

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