Публікація: General Testing Models of SOC Hardware Software Components
dc.contributor.author | Hahanov, V. I. | |
dc.contributor.author | Litvinova, E. I. | |
dc.contributor.author | Gharibi, W. | |
dc.date.accessioned | 2016-09-02T06:48:00Z | |
dc.date.available | 2016-09-02T06:48:00Z | |
dc.date.issued | 2008 | |
dc.description.abstract | Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown. | uk_UA |
dc.identifier.citation | Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96. | uk_UA |
dc.identifier.uri | http://openarchive.nure.ua/handle/document/1954 | |
dc.language.iso | en | uk_UA |
dc.publisher | KNURE | uk_UA |
dc.subject | Infrastructure Intellectual Property | uk_UA |
dc.subject | Register Transfer Graph | uk_UA |
dc.subject | System-on-a-Chip | uk_UA |
dc.subject | Testing | uk_UA |
dc.title | General Testing Models of SOC Hardware Software Components | uk_UA |
dc.type | Article | uk_UA |
dspace.entity.type | Publication |
Файли
Оригінальний пакет
1 - 1 з 1
Завантаження...
- Назва:
- Хаханов_РИ_2008_1ENGLISH.pdf
- Розмір:
- 1.05 MB
- Формат:
- Adobe Portable Document Format
Ліцензійний пакет
1 - 1 з 1
Немає доступних мініатюр
- Назва:
- license.txt
- Розмір:
- 9.42 KB
- Формат:
- Item-specific license agreed upon to submission
- Опис: