Публікація: Coverage Method for FPGA Fault Logic Blocks by Spares
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Дата
2009
Назва журналу
ISSN журналу
Назва тома
Видавництво
EWDTS
Анотація
A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The problem of testing technologies adaptation for new digital system-in-package (SiP), which gradually develops the market of electronic technology [1-6] is considered. SiP forms new challenges of real-time Infrastructure IP for system functionalities, which differs from embedded diagnosis of SoC components essentially. Yervant Zorian is leading scientist in the field of Design and Test in the world [3] and he said now the main problem of digital system repairing is designing the methods and technologies for on-chip logic repairing although it occupies no more 10% of chip area. Objective of the research is design of a method for on-chip diagnosis of digital system-on-a-chip on the basis of traversal the rows and columns to increase SiP testability, quality and reliability. The problems are: 1) design of a matrix model for the FPGA logic blocks in the form of tiles, which contain faults; 2) design of a coverage method for faulty logic blocks by spare tiles in the traversal of matrix rows or columns; 3) testing and verification of the method on examples of logic block matrixes, containing various faulty configurations.
Опис
Ключові слова
Coverage Method, FPGA, Fault Logic Blocks by Spares
Бібліографічний опис
Vladimir Hahanov Coverage Method for FPGA Fault Logic Blocks by Spares /Vladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)