Програмне середовище MOSI HDL для моделювання векторно-логічних структур

Abstract

This work introduces the MOSI HDL software environment for simulating combinational Verilog circuits. The environment supports generating high-value simulation results, fault matrices, and fault tables, along with both textual and schematic representations of the circuit. Good-value simulation (GVS) is implemented using an address-based lookup table (LUT) in vector form [1]. The fault matrix is generated using the Fault-as-Address Simulation (FAAS) method [2]. The fault table contains integral scores that reflect the circuit's test coverage [3]. Tables and schematics are cross-referenced within an integrated interactive environment, enabling coordinated exploration of simulation and fault-analysis results