Спільне проєктування апаратно-програмного забезпечення вбудованих систем в САПР Vivado Design Suite та Vitis Unified IDE

Abstract

The paper considers the methodology of hardware/software co-design for embedded systems based on SoC, particularly the use of Vivado Design Suite and Vitis Unified IDE tools from AMD. As an example, a model of a multifunctional wristwatch based on SoC Zynq7000 (on the board EBAZ 4205) was created, which includes both hardware and software parts. The project for the FPGA part was described in VHDL using a single pre-designed IP core in Vivado. In parallel, a project that defines the control of the display was created in C language in Vitis. The experimental results confirmed the correctness of the model and the feasibility of using these tools for hardware/software co-design of embedded systems.