Особенности использования языков описания аппаратуры VHDL И Verilog

Abstract

VHDL and Verilog are hardware descriptive languages. These languages are designed for simulate electronic circuits at the level of valve, register transmissions, microcircuit cases. Therefore, they can be called languages of through fвпunctional and logical design. However, they have a number of differences, which we will consider in this article