Реалізація алгоритму ldpc кодування за допомогою ПЛІС

Abstract

This work is devoted to usage of error-prof low density parity check codes and how algorithm of coding information can be optimized and implemented using FPGA. Because FPGA gives opportunity to parallelize computations and optimize algorithms, it can produce codding much more faster instead of using CPU. Also generator matrix for low density parity check codes can be generated so that can be stored in shift registers. It allows not to store full generator matrix but store only parts of it. To restore the rest of the matrix, it is only necessary to perform a cyclic shift operation.