ElAr :: Перегляд за автором "Hahanov, V. I."

Перегляд за автором "Hahanov, V. I."

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A Diagnostic Model for Detecting Functional Violation in HDL-Code of System-on-Chip
(EWDTS, 2011) Umerah, N. C.; Hahanov, V. I.
The problem of synthesis or analysis of the components of any system can be formulated by the interaction of its model with input patterns and reactions in a space. This is similar to determining the symmetric difference of the three components – model, test patterns and reaction of the model when the test pattern is applied to it. The distance or relationship between two or more objects in a space can be determined by the well known Cartesian or polar coordinate systems. In case of Boolean variables the Hamming distance has been used to determine how close or far apart are two binary variables of any length. Using Hamming distance results in cardinality or a number; but the beta metric proposed in this paper gives a broader view of how two or more binary variables of any length relates to each other in a cyberspace. And Hamming distance is only a particular case of beta metric. In this paper we define cyberspace as a set of interacting information processes and phenomena which conforms to a predefined metric using computer systems and networks as a vehicle. This paper is organised as follows: In section 2 we discuss the beta metric used in defining the relationship between objects in a space. The analysis of interactive graph of components of technical diagnostics is presented in section 3 followed by a model to search for functional violation in HDLcode in section 4.
A WSN Approach to Unmanned Aerial Surveillance of Traffic Anomalies: Some Challenges and Potential Solutions
(EWDTS, 2012) David Afolabi; Ka Lok Man; Hai-Ning Liang; Eng Gee Lim; Zhun Shen; Chi-Un Lei; Tomas Krilavičius; Yue Yang; Lixin Cheng; Hahanov, V. I.; Yemelyanov, Igor
Stationary CCTV cameras are often used to help monitor car movements and detect any anomalies— e.g., accidents, cars going faster than the allowed speed, driving under the influence of alcohol, etc. The height of the cameras can limit their effectiveness and the types of image processing algorithm which can be used. With advancements in the development of inexpensive aerial flying objects and wireless devices, these two technologies can be coupled to support enhanced surveillance. The flying objects can carry multiple cameras and be sent well above the ground to capture and feed video/image information back to a ground station. In addition, because of the height the objects can achieve, they can capture videos and images which could lend themselves more suitably for the application of a variety of video and image processing algorithms to assist analysts in detecting any anomalies. In this paper, we examine some main challenges of using flying objects for surveillance purposes and propose some potential solutions to these challenges. By doing so, we attempt to provide the basis for developing a framework to build a viable system for improved surveillance based on low-cost equipment. With the cost of cars decreasing, more and more people are opting to use cars as their main means of transportation. In cities with large populations, the exponential rise in the number of cars on the streets can lead to many issues (e.g., accidents, congestions, etc.). Governments are spending large amounts of resources in order to improve means to help monitor the movement of cars and in the process enable enforcement officers detect any existing anomalies and prevent potential ones. One widespread technology used to monitor the flow of cars is CCTVs. These can be seen placed on top of street light posts, traffic lights and/or specialized street structures. Although useful, these types of structures are limited in their height, and this limitation can constraint severely the kinds of images and videos can be captured. Similarly, the type of images and videos can determine to a large extent how well they support computer vision and image analysis algorithms. We believe that the use of unmanned flying (or aerial) vehicles (UAV) embedded with video cameras and wireless devices to be used in conjunction with normal CCTVs can support enhanced monitoring of car movements. Unmanned flying objects have become inexpensive and so have video cameras and wireless devices. In this paper, we explore some challenges of using these technologies for automatic monitoring of car flows and suggest some potential solutions for researchers to consider.
Algebra-Logical Repair Method for FPGA Logic Blocks
(ХНУРЭ, 2009) Hahanov, V. I.; Gharibi, W.; Guz, O. A.; Litvinova, E. I.
An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the operability of FPGA blocks and digital system as a whole. It enables to obtain exact and optimal solution associated with the minimum number of spares needed to repair the FPGA logic components with multiple faults.
Assertions-based mechanism for the functional verification of the digital designs
(EWDTW, 2005) Hahanov, V. I.; Yegorov, O.; Zaychenko, S.; Parfentiy, A.; Kaminska, M.; Kiyaschenko, A. V.
According to [1] the verification cost of the digital devices, designed on the base of ASIC, IP-core, SoC technologies, takes up to 70% of the overall design cost. Similarly, up to 80% of the project source code implements a testbench. Reducing these two mentioned parameters minimizes timeto-market, and this is one of the main problems for the world-leading companies in the area of Electronic Design Automation (EDA). The goal of the verification tasks is to eliminate all design errors as early as possible to meet the requirements of the specification. Passing the error through the subsequent design stages (from a block to a chip, and later to a system) each time increases the cost of it’s elimination. Validation – a higher-level verification model – confirms the correctness of the project against the problems in the implementation of the major specified functionality. The goal of this paper is to noticeably decrease the verification time by extending the design with software-based redundancy – the assertions mechanism [2-5], which allows to simply analyze the major specified constraints during the device simulation process and to diagnose the errors in case of their detection. To achieve the declared goal it is necessary to solve the following problems: 1. To formalize the assertions-based product verification process model. 2. To develop the software components for synthesis and analysis of the assertions for the functionality, blocks and the entire system. 3. To get experimental confirmation of the benefits from using assertions to reduce time-to-market or, in other words, to noticeably reduce verification and overall design time.
Cloud Traffic Control System
(EWDTS, 2013) Ziarmand, A.; Hahanov, V. I.; Guz, O. A.; Ngene, C. U.; Arefjev, A.
A cloud service “Green Wave” (the intellectual road infrastructure) is proposed to monitor and control traffic in real-time through the use of traffic controllers, RFID cars, in order to improve the quality and safety of vehicle movement, as well as for minimization the time and costs when vehicles are moved at the specified routes. The evolution of cyber world is divided into the following periods: 1) the 1980s - formation of personal computers; 2) the 1990s - the introduction of Internet technologies in production processes and people's lives; 3) the 2000s - improving the quality of life through the introduction of mobile devices and cloud services, and 4) the 2010s - the creation of a digital infrastructure for monitoring and control of moving objects (air, sea, ground transportation, and robots). Therefore, in the present market feasible problem is the system integration of monitoring-control cloud service and transport RFID blocks as well as digital tools of road infrastructure for optimal on-line vehicle and traffic control in order to address the social, human, economic and environmental problems. What is the basic of the world cyberspace? – The silicon chip and its analogs. Modern microelectronics enables to create not flat but three-dimensional transistor structures (3D – FinFETs) in 14 nm range, commensurate with the size of the atom. This means the appearance in the near future 3D-System-on-Chip instead of flat structures or system-in-package. The advantages of the chips significantly affect the characteristics of industrial products in terms of: energy consumption, dimensions, performance, cost and quality due to reducing not only the dimension of the components, but also the relationships between them. Thus there arise problems associated with heat removal from the internal area of 3D-chip, as well as the creation of new technologies for designing, verification, testing, diagnosis and repairing of its components. Thus, a microworld of cyberspace goes in 3Dmeasurement not easily. Macroworld remains flat when components, computers, networks, cloud services of cyberspace are combined into the system. Which arguments could be made for the transfer of the macroworld in 3D-space? They are the following: the compactness of information, the performance of searching in cyberspace, and its dimension. The triangular flat structure of the system where all nodes are adjacent has a major drawback in the two dimensions – for encoding three nodes or edges it is necessary three codes, and this means that one code of two-bit vector is not used. Therefore, the creation of a primitive structure, where all nodes are adjacent and their number is four to make full use of the two bits code space, means re-open an amazing 3D-figure - a tetrahedron! It has six edges or distances, xor-sum of which is equal to zero. When descripting the figure two edges are redundant, which can be used to reduce the volume of information up to 66% during storage and transfer of data. Formation of cyberspace through the use of primitive tetrahedra allows optimizing (minimizing) the ratio of the structural complexity of the space to the average distance between two points. Object of research is technologies for monitoring and management of vehicles integrated with cloud services, based on the use of the existing road infrastructure, RFID, radar and radio navigation. Subject of research: traffic and road infrastructure of Ukraine and its regions, as well as advanced software and hardware RFID systems for monitoring and road management, based on the use of road controllers, global systems for positioning, navigation (GPS, GPRS), and cloud services in the Internet. The essence of research is creation of intellectual road infrastructure (IRI) – cloud service "Green Wave" for monitoring infrastructure and management of road in real-time, based on creating virtual road infrastructure (Fig. 2), integrated with road traffic controllers, RFID of vehicles in order to improve the quality and safety of vehicle movement, minimization of time and costs when realization of routes.
Coverage Method for FPGA Fault Logic Blocks by Spares
(EWDTS, 2009) Hahanov, V. I.; Litvinova, E. I.; Gharibi, W.; Guz, O. A.
A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The problem of testing technologies adaptation for new digital system-in-package (SiP), which gradually develops the market of electronic technology [1-6] is considered. SiP forms new challenges of real-time Infrastructure IP for system functionalities, which differs from embedded diagnosis of SoC components essentially. Yervant Zorian is leading scientist in the field of Design and Test in the world [3] and he said now the main problem of digital system repairing is designing the methods and technologies for on-chip logic repairing although it occupies no more 10% of chip area. Objective of the research is design of a method for on-chip diagnosis of digital system-on-a-chip on the basis of traversal the rows and columns to increase SiP testability, quality and reliability. The problems are: 1) design of a matrix model for the FPGA logic blocks in the form of tiles, which contain faults; 2) design of a coverage method for faulty logic blocks by spare tiles in the traversal of matrix rows or columns; 3) testing and verification of the method on examples of logic block matrixes, containing various faulty configurations.
Cyber Physical System – Smart Cloud Traffic Control
(EWDTS, 2014) Hahanov, V. I.; Wajeb Gharibi; Abramova, L. S.; Chumachenko, S. V.; Litvinova, E. I.; Hahanova, A. V.; Rustinov, V.; Miz, V.; Zhalilo, A.; Ziarmand, A.
A cyber physical system for smart cloud traffic control is proposed. It is an intellectual (smart) road infrastructure for monitoring and control of traffic in real-time through the use of global systems for positioning and navigation, mobile gadgets and the Internet in order to improve the quality and safety of vehicle movement, as well as for minimizing the time and costs when vehicles are moved at the specified routes. The main innovative idea is step-by-step transfer of traffic lights from the ground to a virtual cloud space for vehicle management, equipped with a mobile gadget or computer, which displays on the screen map, route, coordinates of the road user and real traffic signals. A set of innovative technologies to address the social, humanitarian, economic, energy, insurance, crime and environmental problems through the creation and application of cloud-based digital traffic monitoring and management is developed. All of these technologies and functional components are integrated into the system automaton model of cyber physical system for interaction between an infrastructure cloud of exact monitoring and digital control and vehicle gadget or computer.
Cyber-Physical Emerging Computing
(Харьковский национальный университет радиоэлектроники, 2018) Hahanov, V. I.; Ka Lok Man; Gharibi, W.; Hahanova, A. V.; Litvinova, E. I.
The main trends of the development of the cyber- physical structure presented in Gartner's Hype Cycle 2017 are described to apply them in science, education, transport, industry and state structures. Prospective directions of the market-feasible technologies, related to green cyber-social monitoring and management of society, are proposed. An expanded description of technologies focused on the creation of the smart digital world, green cities and 5G telecommunications is performed. Recommendations are given for using the top 10 technologies of 2017 in business, scientific and educational processes of higher education.
Cybercomputer for Information Space Analysis
(EWDTS, 2011) Litvinova, E. I.; Hahanov, V. I.; Gharibi, W.; Park, Dong Won
This article describes an infrastructure and technologies for analyzing information space, based on virtual cybercomputer. A model and metrics for cyberspace, where subjects are the interacting processes or phenomena with the physical carrier in the form of computer systems and networks, are proposed. The structural model of high-speed multimatrix processor designed for fast and accurate search of information objects in cyberspace is described. Purpose of this article is creation of the individual and virtual computer in cyberspace for intelligence transactions of data and services, focused on each person. The problems are: 1) Defining the functional infrastructure for virtual PCC. 2) Creating a structured database for storing information and services. 3) Developing a PCC template as a set of related services and tools focused to the needs of the user. 4) Developing a system for protection of personal cyberspace, data and services, including authentication, keys, digital signature, cryptography. 5) Creating intelligent tools for searching, pattern recognition and decision making as a set of filters, focused to a specific user. 6) Developing PCC prototype and its testing for different kinds of users. 7) Offering prototype to the companies, which have access to the market of electronic technologies, as well as public relations through Internet, TV, conferences and seminars. References: Cyberspace and its analysis for searching information [1-5]; Hardware engines for high-speed information retrieval [6-10]; Synthesis of computer structures and functionalities [11-13]. The essence of the research is creation of the infrastructure for optimal organization of the individual cyberspace as a virtual computer with the following services: 1) e-mail and telephony; 2) Internet-browsers for searching, recognition and decision making; 3) audio and video players; 4) text and sound editors; 5) electronic banking and shopping; 6) individual business browser for the organization of working days; 7) browser for the management of holidays, culture and sport; 8) traveling browser; 9) structured relational database to store the history and all types of data; 10) external interface Public Relations; 11) medical care and services; 12) comprehensive security system for information and services.
Design and Optimization of a Planar UWB Antenna
(EWDTS, 2013) Lim, Eng Gee; Wang, Zhao; Juans, Gerry; Man, Ka Lok; Zhang, Nan; Hahanov, V. I.; Litvinova, E. I.; Chumachenko, S. V.; Mishchenko, A.; Dementiev, S.
In this paper, we present our design on a simple, low-profile wideband planar antenna with a pure circular radiator fed by a 50 Ω microstrip line. By investigating the feeding position and ground plane dimensions, the antenna is optimized to have a very wide bandwidth that covers the whole FCC-allocated ultra-wideband (UWB) spectrum. Because of the additional patch beneath the radiator, the bandwidth can be further extended towards the lower side of the frequency spectrum. This antenna is finally modified to have a bandwidth from 2 to 12 GHz, which satisfies system requirements for S-DMB, WiBro, WLAN, CMMB and the entire UWB with S11 < -10dB. Since the Federal Communications Commission (FCC) of United States allocated the unlicensed frequency spectrum from 3.1 GHz to 10.6 GHz for commercial applications of ultra-wideband (UWB) technology in 2002 [1], ultra-wideband (UWB) technology has gained great popularity in research and industrial areas because of its high data rate wireless communication capability for various applications. As a crucial part of the UWB system, UWB antennas have been investigated extensively by researchers and numerous proposals for UWB antenna designs have been reported [2-5]. In [2], a new ultra-wideband antenna consisting of two steps, a single slotted patch and a partial ground plane is designed to operate from 3.2 to 12 GHz. In J. N. Lee’s work [3], an ultrawideband antenna composed of a modified trapezoidal radiating patch, a PI-shaped matching stub, CPW feeding, and two steps for impedance matching has been proposed for UWB applications. In [4], an ultrawideband microstrip-fed monopole antenna with a narrow slit and a modified inverted U-slot on the patch is presented. Recently, a small planar antenna fed by a microstrip line has been investigated and designed to exhibit dualband operation for Bluetooth (2.4 - 2.484 GHz) and UWB (3.1 - 10.6 GHz) bands [5]. However, many of the proposed designs employed slots or other complicated modifications in the antenna radiator and/or ground plane. These designs may pose complications during fabrication of the antenna since the tolerance of the increased special features/variables could be problematic when it goes to mass production, and instability due to the fact that complicated antenna structures may also occur in practice. Therefore, we are motivated to design a low complexity, low cost and compact antenna with wide frequency coverage supporting various applications such as Satellite Digital Multimedia Broadcasting (S-DMB), Wireless Broadband (WiBro), Wireless Local Area Network (WLAN), China Multimedia Mobile Broadcasting (CMMB) and UWB. In this paper, we present a very simple circular planar antenna with operating bandwidth ranging from 2 GHz to 12 GHz by integrating several techniques into one compact antenna. The design approach is very similar to our previously reported paper [6]. We start with a simple circular planar antenna fed by a 50Ω microstrip line with a truncated ground plane. Next, based on the study of the size of the radiator and current distribution, the antenna is designed to have an operating bandwidth covering the entire UWB band, i.e. 3.1 - 10.6 GHz. Then, the study on the size of the partial ground plane is conducted to increase the bandwidth towards the lower side of the frequency spectrum, to cover the bands for WLAN (2.4 - 2.484 GHz) and CMMB (2.635 – 2.66 GHz). With an extra patch printed on the back side of the substrate, underneath the circular radiator, the bandwidth can be further increased to cover Wibro (2.3 - 2.4 GHz) and S-DBM (2.17 -2.2 GHz) without significantly influencing other frequency bands. Thus the proposed antenna can be used for various applications such as SDMB, Wibro, WLAN, CMMB and the operating bands are evaluated using with the criterion of having return loss S11 less than 10 dB. Simulated radiation patterns over the whole frequency bands are acceptable.
Design of Wavelet Filter Bank for JPEG 2000 Standard
(EWDTW, 2006) Hahanova, I. V.; Fomina, E.; Sorudeykin, K.; Hahanov, V. I.; Bykova, V.
Models, method and hardware implementation of lifting-based wavelet filter scheme for JPEG 2000 standard are proposed. JPEG 2000 image compression standard is used for data transmission, print and scan of images, digital photography. Low-pass and highpass filters for implementing JPEG 2000 transformation are described. Obtained results were compared with the same parameter of other discrete wavelet transformation (DWT) devices that were proposed in others references. This work purpose is essential speed growing of the ad hoc pipelining lifting-based DWT hardware implementation. JPEG2000 is new image compression algorithm based on discrete wavelet transformation of input data. This technique is a next development of JPEG group. It could be used for data transmitting in Internet, for image printing and scanning, for digital photography. Transform time reduce due to ad hoc SoC architectures essential increases the device feasibility attractiveness. To achieve this purpose the next challenges have been solved: 1. Digital models and their transformation methods were considered. 2. Lifting-based wavelet transformation hardware architecture was designed. 3. Control algorithm for DWT was created. 4. DWT-device on Xilinx FPGA was implemented. 5. Digital system testing and verification, different device version speeds and SNR were compared. Discrete wavelet transformation device architecture, which doesn’t use external memory that increase the device speed, was developed. Also it allows reducing device cost. IP Core for JPEG2000 encoder/decoder SoC was proposed. In this work it was put emphasis on the fast control block design, not only arithmetic blocks that was made in considering references. It allows increasing speed the whole device. The speed analysis for devices implemented on different Xilinx FPGA series with different memory types and transformation image sizes was done. The device was compared with existing prototypes by speed and area. Scientific novelty is the pipelining DWT device that is intent to use as IP core and implement in programmable chip. The proposed device has more simple ALU part, doesn’t use external memory, and so is faster and chipper than existing analogs. The practical significance is proposition of the simple, high technology and effective DWT device that have high speed and low power consumption. It is its advantage in over software implementation of the IEEE JPEG2000 standard. Further work steps: 1. DWT and IDWT device design for 5/3 and 9/7 JPEG2000 filter banks. 2. DWT and IDWT device implementation using Xilinx Virtex-4 DSP processor.
Diagnosis of SoC Memory Faulty Cells for Embedded Repair
(EWDTS, 2008) Litvinova, E. I.; Hahanov, V. I.; Krasnoyaruzhskaya, K.; Galagan, S.
A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It enables to obtain minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in the form of memory rows and columns. Modern digital systems-on-chip (SoC) include millions of equivalent gates and new high-level design technologies are necessary for their creation [1-3]. SoC memory in the future will occupy more than 90% of chip area that is oriented on use flexible software [3- 7,11]. Development of models and methods of quick and exact diagnosis, as well as technologies for repair of faulty cells by on-chip facility in real time and on all life cycle stages of a product are urgent problems. It will enable to decrease quantity of chip pins, to raise yield, to decrease time-to-market, to reduce service costs, as well as to remove output diagnosis and repair facility [1,6,7,12]. The research aim is development of algebra-logical method of embedded matrix memory diagnosis and repair in real time. The problems: 1) Analysis of SoC Infrastructure Intellectual Property Technologies; 2) Development of an Infrastructure Intellectual Property method on basis of the covering matrix; 3) Formalization of the algebralogical AL-method for embedded memory repair; 4) Analysis of obtained results. Modern design technologies of digital systems on chips propose along with creation of functional blocks F-IP development of service modules I-IP, which are oriented on complex solving of the project quality problem and yield increasing in manufacturing that is determined by implementation of the following services into a chip [11,14,16]: 1) Diagnosis of failures and faults by analysis of information, which is obtained on the stage of testing and use of special methods of embedded fault lookup on basis of the standard IEEE 1500 [8,13,15]; 2) Repair of functional modules and memory after fixation of a negative testing result, fault location and identification of a fault type in carrying out of the diagnosis phase; 3) Measurement of the general characteristics and parameters of a device operation on basis of on-chip facilities, which enable to make time and volt-ampere measurements; 4) Reliability and fault tolerance of a device operation in working that is obtained by diversification of functional blocks, redundancy of them and repair of SoC in real time.
General Testing Models of SOC Hardware Software Components
(KNURE, 2008) Hahanov, V. I.; Litvinova, E. I.; Gharibi, W.
Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.
HES-MV – A Method for Hardware Embedded Simulation
(EWDTW, 2006) Hahanov, V. I.; Krasovskaya, Anastasia; Boichuk, Maryna; Gorobets, Oleksandr
Hardware implementation of triadic fault-free simulation method HES-MV – Hardware Embedded Simulation based on Multi-Valued alphabet is proposed. This method uses hardware gate and RTL models for large scale digital designs description. Structure solutions for logic elements models implementation are presented. Logic element has two bits for four values encoding for each input or output line of simulated device. Necessity for considerable increase of simulation performance for testing and verification purposes is well-known, it is defined by increasing complexity of digital system-on-chips with millions of gates. Existing simulation tools of leading companies: Cadence, Mentor Graphics, Synopsys, Aldec, spend several hours to analyze design with several millions of gates (PC with 500MHz microprocessor and 512MB RAM). Such costs are very important for end users. Aldec Inc. (www.aldec.com) proposes one of the possible solution: during system verification, separate design model on two parts (hardware H and software S): M={H,S}, H>>S. Moreover software model – a new one, unverified source code. Hardware part is tested IP –cores, implemented into HES (Hardware Embedded Simulator), based on Xilinx’s FPGA, connected to the simulation kernel through PCI interface. Thus, Aldec proposed new design flow for world market, it gives possibility to reduce verification time in ten times. But hardware-based simulation excludes possibility for multi-valued simulation mode and transition analysis, hazard simulation, races analysis as well. Proposed approach, along with preserving hardware simulation advantages in performance, allows to simulate signal races and to solve set-up problem by extending hardware model with two-bit signals to identify four states of logic variable. Proposed bus-based primitive and logic elements hardware models may be important on world market of electronic design automation tools for design and test of large scale digital devices. Object of inquiry – digital circuit, implemented into ASIC of PLD, specified using VHDL language. Goal of the research – considerable decrease digital device design time (which will be implemented into integrated circuit, containing millions of gates) and extend functional capabilities of fault-free simulation system by multi-valued models hardware implementation, high-performance simulation method for set-up problem solving, race analysis and timing verification of tests under synthesis. Research problems: 1. Digital circuit models classification. 2. Multi-valued analysis model for hazard detection and set-up problem solving. 3. Creation of software/hardware tools structure to multi-valued fault-free simulation. 4. Software/hardware implementation of multi-valued fault-free simulation method. 5. Testing and verification of hardware/software HES-MV tool.
Hierarchical Analysis of Testability for SoCs
(EWDTW, 2006) Kaminska, M.; Hahanov, V. I.; Kulak, E.; Guz, O. A.
This paper presents the strategy of testable SoC design procedure. This approach based on the testability analysis on different levels of abstractions (gate level, register transfer level, system level). Analysis is based on structural analysis of SoC. Proposed methods give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The main goal of the presented algorithms is to increase fault coverage before test generation and to decrease verification time. It could be reached by improving of testability and simplification of the verification task. As a complexity of today’s ASIC designs continues to increase, the challenge of verifying these designs intensifies at an even greater rate [1]. Testability is one of the most important factors that are considered at digital devices design along with reliability, speed and the cost. The low level of device testability leads to increasing of number of non-tested faults and verification time at design, production and operations stages. Therefore, the cost of diagnostic (a degree of faults concentration) decreases essentially during techniques of testability design. The cost of a fault essentially increases in the process of ASIC crystal implementation (Fig. 1). Hence analysis of testability needs to be done at earlier level of device description. This is the main reason of development of the methods of testability analysis at the different levels of abstraction: system, RT, and gate levels. Object under test – system on chip, which can be presented on different levels of abstraction. Goal of work – maximal decreasing of test procedure cost; to provide digital circuit testability on all design levels of abstraction, till device manufacturing stage. To provide device testing possibility with minimal test by adding of scan cells on bottlenecks in circuit (circuit’s parts, which hard to test).
Hierarchical Systems Testing based on Boundary Scan Technologies
(EWDTW, 2006) Hahanov, V. I.; Melnik, D.; Yeliseev, V.; Hahanova, A. V.
We propose models of complex program-technical systems testing; these models solve diagnosis tasks in real time. Models use IEEE standard boundary scan technologies to observe internal lines, and methods of testability evaluation to define critical places in digital objects. Models and methods are oriented to test distributed control systems of critical technologies. Basic requirements for modern informational and control systems for complex objects and critical technologies are: 1) provide high reliability during operation; 2) online monitoring and control of all the parameters of critical system of object; 3) testing, diagnostics and repair in technically and standard acceptable time; 4) provide desired diagnosis depth of system or its components, automatically and in real time. New generation of modern technologies and design flows introduces additional criteria, related to design, manufacture and operation of digital devices: time-tomarket, Design-for-Manufacturability, Testability, Diagnosis, Verification. Major design stage is verification process, aimed to eliminate all design errors on the early stages; it leads to considerable time and costs savings. Acceptable testable overhead (assertion), added at early design stage, is interesting here, because it considerable decreases main parameter – time-to-market, using verification and testing methods; it is very urgent and attractive design model. Talk is about use of verification test, obtained at system design stage, to check device with minimal additional hardware and software expenses using boundary scan technologies. At the same time, hardware/software overhead mechanism must include additional control points, which must be introduced into design using Boundary Scan Register of special (ad-hoc) technologies at synthesis stage. As a result, design redundancy created once maybe used many times to check components of digital system during all stages of its lifecycle. At present, complex digital devices are considered as objects with several levels of hierarchy. At the lowest level, system is represented as a set of modern integrated circuits (PLD, ASIC), which implements SoCs, NoCs, memory, processors. Second level is formed by system on boards, where integral circuits are represented as primitives. Third level represents set of boards, which integrated into crates. Fourth level combines set of crates or boxes into complex distributed control system of technological process, manufacturing or critical technologies (aviation, cosmonautics, nuclear-power engineering, meteorology, defense, ecology). Fifth level may be considered as geographically distributed system, e.g. Internet. In this research, we consider from first to fourth levels of hierarchy, in order to creation of models and methods of its testing with defined diagnosis depth. Research objective – considerable decrease of complex digital system testing time during operation based on creation of general model of organization and execution of diagnostic experiment, including unconditional algorithms of faults finding using IEEE standards of testable design. Research problems: 1) choosing appropriate methods and tools for testing of all mentioned levels of hierarchy; 2) development of hierarchical model of organization and execution of diagnostic experiment, including conditional and unconditional algorithms of faults finding, oriented to testable design standards; 3) practical implementation of complex digital devices testing models and experimental evaluation.
Infrastructure for Testing and Diagnosing Multimedia Devices
(EWDTS, 2011) Hahanov, V. I.; Mostova, K.; Paschenko, O.
In this paper HW/SW systems testing and faults diagnosing approach is described, also method for effective faults detection and defects localization within the systemunder-test is proposed. Essential increase of consumer requirements for complex electronic devices leads to substantial growth of complexity for HW and SW components, services, and system interfaces. Such tendency increases the importance to provide high quality for HW, SW, and networking components and services. One of the main goals which comes to the foreground of industry is to decrease the cost of exploitation by creating the standardized infrastructures for maintenance which providing service exploitation, testing, disposal and, elimination of functional defects. Well known rule of ten for hardware components stating that fault detection cost increases in ten times on the next following design or manufacturing stages. Nowadays fast growing complexities of hardware is transforming this rule into rule of twenty which makes even more important to detect the fault on early design stages, rather then on chip/PCB manufacturing, or system assembling stages. Goal of this work is to develop method which increases product quality by means of developing sufficient HW/SW test and diagnosis approach, also decreasing faults detection and defects localization time in order to improve system performance on example of multimedia devices.
Internet of Things: A Practical Implementation based on a Wireless Sensor Network Approach
(EWDTS, 2012) Mercaldi, Michele; D’Oria, Andrea; Murru, Davide; Liang, Hai-Ning; Man, Ka Lok; Lim, Eng Gee; Hahanov, V. I.; Mischenko, A.
In this paper we present an introduction and an overview of the Internet of Things concept and its possible realization of an infrastructure based on a Wireless Sensor Network. Our proposed solution aims for memory and power consumption efficiency. Similarly, our proposed implementation is informed by (1) open technology standards; (2) accessibility and reachability; and (3) multi functionality and modularity. In addition, we place emphasis on the use of very low power devices and communication protocols. Internet of Things (IoT), a term first coined by Kevin Ashton in 1999 , is used to refer to uniquely identifiable objects (or more broadly things) and their virtual representations, similar to the network of websites in an internet. The idea is to have all things tagged and, if that were the case, they could be identified and inventoried by computers. If this could be implemented, it will transform drastically our way of life —waste will be reduced significantly; stores will not run out of stock; and stolen items could be easily located. A main component of IoT infrastructure is “smart objects” which are objects that hold a unique identifier. The identifier will allow the objects to be located, enable them to interact with their surrounding environment, and let them communicate with each other for data exchange and collaboration. Within the IoT paradigm, smartness is not only for objects but includes the nature of the networks that connect them. To build smart objects, we need sensors, actuators, radio-frequency identification (RFID) tags, etc. Applications of IoT include domotics, industrial application, nature and environmental monitoring. Even after more than a decade since it was first coined, the implementation of a system of IoT has yet to become a reality. In this paper we proposed a plausible implementation of an IoT system or infrastructure based on a wireless sensor network (WSN) approach. We propose hardware and software possibilities to support such an infrastructure.
Matrix Manipulation Algorithms for Hasse Processor Implementation
(EWDTS, 2014) Hahanov, V. I.; Dahiri Farid
Models and Methods for Verification and Diagnosis of SoC HDL-code
(ХНУРЭ, 2010) Hahanov, V. I.; Gharibi, W.; Litvinova, E. I.; Chumachenko, S. V.
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.

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