Методи реалізації архітектури сумісного тестування вбудованих систем на кристалі з використанням високорівневого синтезу

Abstract

Modern system-on-chip platforms combine processor subsystems and programmable logic, enabling efficient implementation of embedded signal processing algorithms. However, the heterogeneous architecture of such systems complicates verification and testing. This paper considers methods for implementing a co-testing architecture for SoC-based embedded systems using high-level synthesis (HLS). The proposed approach enables integrated verification of software models and synthesized hardware modules through functional simulation, hardware–software co-simulation, and validation on the target SoC platform, ensuring consistency between software and hardware implementations