Дослідження впливу заходів щодо забезпечення тестопридатності цифрових керуючих автоматів на апаратурні витрати

Abstract

Problems of minimal additional hardware costs during design automation of easy-testable digital finite state machines (FSM) are considered. The reasonable way of the FSM setting into an arbitrary state is to expand the state table, which improves the controllability of FSM' states and leads to the transformation of their HDL-models. Hardware costs for different methods of hardware redundancy introduction to HDL-models of finite state machines are estimated.