Design of real-time system logic control on FPGA

Публікація:
Design of real-time system logic control on FPGA

dc.contributor.author	Myroshnyk, M.
dc.contributor.author	Shkil, O. S.
dc.contributor.author	Kulak, E.
dc.contributor.author	Rakhlis, D.
dc.contributor.author	Filippenko, I.
dc.contributor.author	Hoha, M.
dc.contributor.author	Malakhov, M.
dc.contributor.author	Sergienko, V.
dc.date.accessioned	2020-06-04T18:21:45Z
dc.date.available	2020-06-04T18:21:45Z
dc.date.issued	2019
dc.description.abstract	Problems of real-time hardware logic control systems design on the FPGA are considered. The control algorithm is implemented based on a timed FSM model,represented by a temporal state diagram. The design of the control device model using hardware description language VHDL in the form of the three-process pattern is made. The functional verification of the model was carried out using Active-HDL tools, the synthesis of the circuit was carried out on the Spartan 3E FPGA technology platform using Xilinx ISE CAD tools. The hardware costs for the circuit implementation of the control device were analyzed.	uk_UA
dc.identifier.citation	Design of real-time system logic control on FPGA / M. Myroshnyk, O. Shkil, E. Kulak , etc. // 2019 IEEE EWDTS. – 2019. – №16. – С. 488–491.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/11996
dc.language.iso	en	uk_UA
dc.subject	timed FSM	uk_UA
dc.subject	temporal state diagram	uk_UA
dc.subject	functional verification	uk_UA
dc.subject	pattern	uk_UA
dc.title	Design of real-time system logic control on FPGA	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication