Models and Methods for Verification and Diagnosis of SoC HDL-code

Публікація:
Models and Methods for Verification and Diagnosis of SoC HDL-code

dc.contributor.author	Hahanov, V. I.
dc.contributor.author	Gharibi, W.
dc.contributor.author	Litvinova, E. I.
dc.contributor.author	Chumachenko, S. V.
dc.date.accessioned	2016-09-02T08:41:04Z
dc.date.available	2016-09-02T08:41:04Z
dc.date.issued	2010
dc.description.abstract	Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.	uk_UA
dc.identifier.citation	Models and Methods for Verification and Diagnosis of SoC HDL-code / V. Hahanov and all // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 36-46.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1980
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	time-to-market	uk_UA
dc.subject	Xor-metrix	uk_UA
dc.subject	verification	uk_UA
dc.subject	HDL-code	uk_UA
dc.title	Models and Methods for Verification and Diagnosis of SoC HDL-code	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication