ElAr :: Перегляд за автором "Litvinova, E. I."

Перегляд за автором "Litvinova, E. I."

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Algebra-Logical Repair Method for FPGA Logic Blocks
(ХНУРЭ, 2009) Hahanov, V. I.; Gharibi, W.; Guz, O. A.; Litvinova, E. I.
An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the operability of FPGA blocks and digital system as a whole. It enables to obtain exact and optimal solution associated with the minimum number of spares needed to repair the FPGA logic components with multiple faults.
Cloud Infrastructure for Car Service
(EWDTS, 2013) Litvinova, E. I.; Englesy, I. P; Miz, V. A; Shcherbin, D.
A set of innovative scientific and technological solutions, including for solving social, human, economic and environmental problems associated with creation and use of a cloud for monitoring and management is developed. All of these technologies and tools are integrated into the automaton model of real-time interaction between monitoring and management clouds, vehicles and road infrastructure. Each car has a virtual model in a cyberspace - an individual cell in the cloud, which is invariant with respect to drivers of vehicles. Where does it go real cyber world? Corporate networks, personal computers, as well as individual services (software), go to the "clouds" of a cyberspace, which have an obvious tendency to partition the Internet for specialized services, Fig.1. If today 4 billion users are connected in the Internet (1 zettabytes = 7021 210 = bytes) by means of 50 billion gadgets, in five years each active user will have at least 10 devices for connecting in cyberspace. Use of personal computers without replicating data to all devices becomes impossible. But even simple copying requires more non-productive time for servicing systems and projects, which can reach 50% if several devices or servers with identical functions are available. Unprofessional (bad) service of such equipment creates problems reliable data retention, as well as unauthorized access. Also, there is a problem of remote access to the physical devices when migrating users in the space, and obtaining the necessary services and information from gadgets left at home or in the office is difficult. Economic factor of effective use of purchased applications installed in gadgets and personal computers, force the user to give up their purchase in favor of almost rent free services in the clouds. All of the above is an important argument and undeniable evidence of imminent transition or the outcome of all mankind to cyberspace of virtual networks and computers, located in reliable service clouds. Advantages of the virtual world lie in the fact that the micro-cells and macro-networks in the clouds are invariant with respect to numerous gadgets of each user or corporation. Cloud components solve almost all of the above problems of reliability, safety, service and practically don't have disadvantages. So far as the corporations and users go to the clouds, protection of information and cyber components from unauthorized access, destructive penetrations and viruses is topical and market appealing problem. It is necessary to create a reliable, testable and protected from the penetrations cyberspace infrastructure (virtual PCs and corporate networks), similar to currently available solutions in the real cyber world. Thus, each service being developed in the real world should be placed in the appropriate cloud cell that combines components similar in functionality and utility. The above applies directly to the road service, which has a digital representation in cyberspace for subsequent modeling all processes on the cloud to offer every driver quality conditions of movement, saving time and money. The goal of the project is improving the quality and safety of traffic through creating intelligent road infrastructure, including clouds of traffic monitoring and quasi-optimal motion control in real-time by using RFID-passports of vehicles, which allow minimizing the time and costs of traffic management and creating innovative scientific and technological solutions of social, humanitarian, economic and environmental problems of the world.
Coverage Method for FPGA Fault Logic Blocks by Spares
(EWDTS, 2009) Hahanov, V. I.; Litvinova, E. I.; Gharibi, W.; Guz, O. A.
A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The problem of testing technologies adaptation for new digital system-in-package (SiP), which gradually develops the market of electronic technology [1-6] is considered. SiP forms new challenges of real-time Infrastructure IP for system functionalities, which differs from embedded diagnosis of SoC components essentially. Yervant Zorian is leading scientist in the field of Design and Test in the world [3] and he said now the main problem of digital system repairing is designing the methods and technologies for on-chip logic repairing although it occupies no more 10% of chip area. Objective of the research is design of a method for on-chip diagnosis of digital system-on-a-chip on the basis of traversal the rows and columns to increase SiP testability, quality and reliability. The problems are: 1) design of a matrix model for the FPGA logic blocks in the form of tiles, which contain faults; 2) design of a coverage method for faulty logic blocks by spare tiles in the traversal of matrix rows or columns; 3) testing and verification of the method on examples of logic block matrixes, containing various faulty configurations.
Cyber Physical System – Smart Cloud Traffic Control
(EWDTS, 2014) Hahanov, V. I.; Wajeb Gharibi; Abramova, L. S.; Chumachenko, S. V.; Litvinova, E. I.; Hahanova, A. V.; Rustinov, V.; Miz, V.; Zhalilo, A.; Ziarmand, A.
A cyber physical system for smart cloud traffic control is proposed. It is an intellectual (smart) road infrastructure for monitoring and control of traffic in real-time through the use of global systems for positioning and navigation, mobile gadgets and the Internet in order to improve the quality and safety of vehicle movement, as well as for minimizing the time and costs when vehicles are moved at the specified routes. The main innovative idea is step-by-step transfer of traffic lights from the ground to a virtual cloud space for vehicle management, equipped with a mobile gadget or computer, which displays on the screen map, route, coordinates of the road user and real traffic signals. A set of innovative technologies to address the social, humanitarian, economic, energy, insurance, crime and environmental problems through the creation and application of cloud-based digital traffic monitoring and management is developed. All of these technologies and functional components are integrated into the system automaton model of cyber physical system for interaction between an infrastructure cloud of exact monitoring and digital control and vehicle gadget or computer.
Cyber-Physical Emerging Computing
(Харьковский национальный университет радиоэлектроники, 2018) Hahanov, V. I.; Ka Lok Man; Gharibi, W.; Hahanova, A. V.; Litvinova, E. I.
The main trends of the development of the cyber- physical structure presented in Gartner's Hype Cycle 2017 are described to apply them in science, education, transport, industry and state structures. Prospective directions of the market-feasible technologies, related to green cyber-social monitoring and management of society, are proposed. An expanded description of technologies focused on the creation of the smart digital world, green cities and 5G telecommunications is performed. Recommendations are given for using the top 10 technologies of 2017 in business, scientific and educational processes of higher education.
Cybercomputer for Information Space Analysis
(EWDTS, 2011) Litvinova, E. I.; Hahanov, V. I.; Gharibi, W.; Park, Dong Won
This article describes an infrastructure and technologies for analyzing information space, based on virtual cybercomputer. A model and metrics for cyberspace, where subjects are the interacting processes or phenomena with the physical carrier in the form of computer systems and networks, are proposed. The structural model of high-speed multimatrix processor designed for fast and accurate search of information objects in cyberspace is described. Purpose of this article is creation of the individual and virtual computer in cyberspace for intelligence transactions of data and services, focused on each person. The problems are: 1) Defining the functional infrastructure for virtual PCC. 2) Creating a structured database for storing information and services. 3) Developing a PCC template as a set of related services and tools focused to the needs of the user. 4) Developing a system for protection of personal cyberspace, data and services, including authentication, keys, digital signature, cryptography. 5) Creating intelligent tools for searching, pattern recognition and decision making as a set of filters, focused to a specific user. 6) Developing PCC prototype and its testing for different kinds of users. 7) Offering prototype to the companies, which have access to the market of electronic technologies, as well as public relations through Internet, TV, conferences and seminars. References: Cyberspace and its analysis for searching information [1-5]; Hardware engines for high-speed information retrieval [6-10]; Synthesis of computer structures and functionalities [11-13]. The essence of the research is creation of the infrastructure for optimal organization of the individual cyberspace as a virtual computer with the following services: 1) e-mail and telephony; 2) Internet-browsers for searching, recognition and decision making; 3) audio and video players; 4) text and sound editors; 5) electronic banking and shopping; 6) individual business browser for the organization of working days; 7) browser for the management of holidays, culture and sport; 8) traveling browser; 9) structured relational database to store the history and all types of data; 10) external interface Public Relations; 11) medical care and services; 12) comprehensive security system for information and services.
Design and Optimization of a Planar UWB Antenna
(EWDTS, 2013) Lim, Eng Gee; Wang, Zhao; Juans, Gerry; Man, Ka Lok; Zhang, Nan; Hahanov, V. I.; Litvinova, E. I.; Chumachenko, S. V.; Mishchenko, A.; Dementiev, S.
In this paper, we present our design on a simple, low-profile wideband planar antenna with a pure circular radiator fed by a 50 Ω microstrip line. By investigating the feeding position and ground plane dimensions, the antenna is optimized to have a very wide bandwidth that covers the whole FCC-allocated ultra-wideband (UWB) spectrum. Because of the additional patch beneath the radiator, the bandwidth can be further extended towards the lower side of the frequency spectrum. This antenna is finally modified to have a bandwidth from 2 to 12 GHz, which satisfies system requirements for S-DMB, WiBro, WLAN, CMMB and the entire UWB with S11 < -10dB. Since the Federal Communications Commission (FCC) of United States allocated the unlicensed frequency spectrum from 3.1 GHz to 10.6 GHz for commercial applications of ultra-wideband (UWB) technology in 2002 [1], ultra-wideband (UWB) technology has gained great popularity in research and industrial areas because of its high data rate wireless communication capability for various applications. As a crucial part of the UWB system, UWB antennas have been investigated extensively by researchers and numerous proposals for UWB antenna designs have been reported [2-5]. In [2], a new ultra-wideband antenna consisting of two steps, a single slotted patch and a partial ground plane is designed to operate from 3.2 to 12 GHz. In J. N. Lee’s work [3], an ultrawideband antenna composed of a modified trapezoidal radiating patch, a PI-shaped matching stub, CPW feeding, and two steps for impedance matching has been proposed for UWB applications. In [4], an ultrawideband microstrip-fed monopole antenna with a narrow slit and a modified inverted U-slot on the patch is presented. Recently, a small planar antenna fed by a microstrip line has been investigated and designed to exhibit dualband operation for Bluetooth (2.4 - 2.484 GHz) and UWB (3.1 - 10.6 GHz) bands [5]. However, many of the proposed designs employed slots or other complicated modifications in the antenna radiator and/or ground plane. These designs may pose complications during fabrication of the antenna since the tolerance of the increased special features/variables could be problematic when it goes to mass production, and instability due to the fact that complicated antenna structures may also occur in practice. Therefore, we are motivated to design a low complexity, low cost and compact antenna with wide frequency coverage supporting various applications such as Satellite Digital Multimedia Broadcasting (S-DMB), Wireless Broadband (WiBro), Wireless Local Area Network (WLAN), China Multimedia Mobile Broadcasting (CMMB) and UWB. In this paper, we present a very simple circular planar antenna with operating bandwidth ranging from 2 GHz to 12 GHz by integrating several techniques into one compact antenna. The design approach is very similar to our previously reported paper [6]. We start with a simple circular planar antenna fed by a 50Ω microstrip line with a truncated ground plane. Next, based on the study of the size of the radiator and current distribution, the antenna is designed to have an operating bandwidth covering the entire UWB band, i.e. 3.1 - 10.6 GHz. Then, the study on the size of the partial ground plane is conducted to increase the bandwidth towards the lower side of the frequency spectrum, to cover the bands for WLAN (2.4 - 2.484 GHz) and CMMB (2.635 – 2.66 GHz). With an extra patch printed on the back side of the substrate, underneath the circular radiator, the bandwidth can be further increased to cover Wibro (2.3 - 2.4 GHz) and S-DBM (2.17 -2.2 GHz) without significantly influencing other frequency bands. Thus the proposed antenna can be used for various applications such as SDMB, Wibro, WLAN, CMMB and the operating bands are evaluated using with the criterion of having return loss S11 less than 10 dB. Simulated radiation patterns over the whole frequency bands are acceptable.
Diagnosis of SoC Memory Faulty Cells for Embedded Repair
(EWDTS, 2008) Litvinova, E. I.; Hahanov, V. I.; Krasnoyaruzhskaya, K.; Galagan, S.
A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It enables to obtain minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in the form of memory rows and columns. Modern digital systems-on-chip (SoC) include millions of equivalent gates and new high-level design technologies are necessary for their creation [1-3]. SoC memory in the future will occupy more than 90% of chip area that is oriented on use flexible software [3- 7,11]. Development of models and methods of quick and exact diagnosis, as well as technologies for repair of faulty cells by on-chip facility in real time and on all life cycle stages of a product are urgent problems. It will enable to decrease quantity of chip pins, to raise yield, to decrease time-to-market, to reduce service costs, as well as to remove output diagnosis and repair facility [1,6,7,12]. The research aim is development of algebra-logical method of embedded matrix memory diagnosis and repair in real time. The problems: 1) Analysis of SoC Infrastructure Intellectual Property Technologies; 2) Development of an Infrastructure Intellectual Property method on basis of the covering matrix; 3) Formalization of the algebralogical AL-method for embedded memory repair; 4) Analysis of obtained results. Modern design technologies of digital systems on chips propose along with creation of functional blocks F-IP development of service modules I-IP, which are oriented on complex solving of the project quality problem and yield increasing in manufacturing that is determined by implementation of the following services into a chip [11,14,16]: 1) Diagnosis of failures and faults by analysis of information, which is obtained on the stage of testing and use of special methods of embedded fault lookup on basis of the standard IEEE 1500 [8,13,15]; 2) Repair of functional modules and memory after fixation of a negative testing result, fault location and identification of a fault type in carrying out of the diagnosis phase; 3) Measurement of the general characteristics and parameters of a device operation on basis of on-chip facilities, which enable to make time and volt-ampere measurements; 4) Reliability and fault tolerance of a device operation in working that is obtained by diversification of functional blocks, redundancy of them and repair of SoC in real time.
General Testing Models of SOC Hardware Software Components
(KNURE, 2008) Hahanov, V. I.; Litvinova, E. I.; Gharibi, W.
Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.
Models and Methods for Verification and Diagnosis of SoC HDL-code
(ХНУРЭ, 2010) Hahanov, V. I.; Gharibi, W.; Litvinova, E. I.; Chumachenko, S. V.
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.
Models for Embedded Repairing Logic Blocks
(EWDTS, 2012) Hahanov, V. I.; Frolov, A.; Litvinova, E. I.; Tiecoura Yves
The models of combinational circuits, focused on solving practical problems of embedded repairing components of the logic units are proposed. The logical circuit is complemented by operational and control automata for modeling digital devices, which increases processing time and hardware costs for creating a wrap of addressable elements. The structures can also be used for hardware modeling functionalities of digital projects by using PLD, which allows improving the performance of software model verification. The proposed solution of embedded gate repair for combinational circuits makes it possible to comprehensively solve the problem of autonomous repairing digital systems on chips due to the time and hardware project redundancy.
Quantum Modeling and Repairing Digital Systems
(EWDTS, 2013) Baghdadi, Ammar Awni Abbas; Hahanov, V. I.; Palanichamy, Manikandan; Litvinova, E. I.; Dementiev, S.
The results of studies concerning the models and methods of quantum diagnosis of digital systems, qubit fault simulation and analysis of fault-free behavior, as well as repair of faulty primitives, are presented.A fault is defined as each individual discrepancy of a product to specification, but fault model should never lead out the product beyond the functionality limits. Therefore fault (fault model – failure) is time fixed part of the functionality that is tied to a physical component. The constant line fault is fixed transition 0- 0 at two adjacent cycles. It makes no sense to consider it as a further extension to other cycles, because according to the automaton model they are all described by means of two adjacent time frames. By extending this two-frame concept to automaton variables we can introduce the full set of fault transitions: 00, 01, 10, 11. Indeed, if we consider the automatic variables, for instance for the register, it is necessary to generate test patterns for verifying the above transitions. Based on the concept of the fault, it follows that the total number of states of functionality also forms a complete set of faults, with the only difference being that the specific fault is always a complement to test signal that detects a fault.
Quantum Models for Description of Digital Systems
(EWDTS, 2013) Hahanov, V. I.; Hahanova, I. V.; Litvinova, E. I.; Priymak, A.; Fomina, E.; Maksimov, M.; Tiecoura Yves; Malek, Jehad Mohammad Jararweh
Quantum models for description of digital systems and results of studies concerning the models and methods of quantum diagnosis of digital systems, qubit fault simulation and analysis of fault-free behavior are presented. Quantum calculators are effectively used for faulttolerant design and solving optimization problems by way of the brute-force method through the use of set theory. A set of elements in the traditional computer is orderly, because each bit, byte or other component has its own address. Therefore, the settheoretical operations are reduced to exhaustive search of addresses of primitive elements. Address order of data structures useful for applications where model components can be strictly ranked, which makes it possible to carry out their analysis in a single pass (a single iteration). If there is not order in the structure, for example, the set of all subsets, the classical model of memory and computational processes disimprove the analysis time of primitive association equal by the rank, or processing of associative groups is ineffective. What can be offered for unordered data instead of the strict order? Processor, where the unit cell is the image or pattern of the universe of n primitives, which generates nQ 2 = all possible states of a cell as a power set or the set of all subsets. Direct solution about creating such cell is based on unitary positional coding states of primitives that form the set of all subsets and in the limit the universe of primitives by superposition of last ones. History of the issue of the necessity for developing quantum computing on the background of the technological revolution in nano-electronics fit in a few of clear theses: 1) Quantum Computer was created the experts in the field of quantum mechanics and electronics, who introduced the idea of creating a non-numeric analogbased computer. 2) The introduced notion of a qubit corresponds to the power set of primitives, which is the ideal nonnumeric form of object component description for analysis, synthesis and optimization of discrete objects. 3) The forms of qubit representation are the following: 1. The universe of primitive symbols, which generate the set of all subsets (power set). 2. Binary vectors, where the power set is a combination of unit values of primitives. 3. Hasse diagram, which forms the power set of all possible solutions on the graph. 4. Full transition graph, which determines the set of all subsets of transitions in the form of arcs. 5. The geometric representation in a plane for a qubit in the form of points and segments corresponding to the Boolean (power set). 4) In practice, more than 90% of all IT-industry problems associated with information retrieval in cyberspace, pattern recognition and decision-making are related to the field of discrete mathematics, where it is difficult to find a place of numerical arithmetic. 5) It is necessary to create associative logic brainlike parallel (quantum) processors, which effectively use Boolean (qubit) primitives or elements (sets) to solve problems of discrete mathematics. 6) Set-theoretic operations have to be replaced the isomorphic logical instructions (and, or, not, xor) for the subsequent creating a new system of parallel qubit programming to solve logic and optimization problems, based on qubit data structures. 7) Another solution for organization computing is associated with topological representation of the qubit, where the elements are the geometric shapes. 8) Nonnumeric problems, focused to the use of quantum processor are the following: minimization of forms of Boolean functions, when describing complex systems; searching paths in the graph; testing and diagnosis of digital systems; combinatorial studies of processes and phenomena; intelligent data searching, pattern recognition and decision making; discretization of fuzzy models and methods, when creating the intelligence; digital data processing and the developing efficient codec for DSP-devices.
Qubit Model for Solving the Coverage Problem
(EWDTS, 2012) Hahanov, V. I.; Litvinova, E. I.; Chumachenko, S. V.; Baghdadi, Ammar Awni Abbas; Eshetie, Abebech Mandefro
Qubit (quantum) structures of data and computational processes for significantly improving performance when solving problems of discrete optimization and fault-tolerant design are proposed. We describe a hardware-focused models for parallel (one cycle) calculating the power set (the set of all subsets) on the universe of n primitives for solving coverage problems, minimization of Boolean functions, data compression, analysis and synthesis of digital systems through the implementation of the processor structure in the form of the Hasse diagram. A prototype of quantum device, implemented by programmable logic, is described. A quantum computer is designed for fault-tolerant design and solving optimization problems by way of the brute-force method through the use of set theory. Considering the discreteness and multiple-valuedness of the alphabets for description of information processes, the parallelism, inherent in the quantum computing, is particularly actual when developing effective and intelligent engines for data retrieval in cyberspace or Internet, tools for synthesis of faulttolerant digital primitives and systems, designing and testing digital systems-on-chips, tools for solving problems of discrete optimization. It does not cover the physical basis of quantum computing, originally planted in the works of scientists, focused on the use of non-deterministic quantum interactions within the atom.
Technology for Faulty Blocks Coverage by Spares
(EWDTS, 2009) Hahanov, V. I.; Chumachenko, S. V.; Litvinova, E. I.; Zaharchenko, O.; Kulbakova, N.
The technology for the minimum coverage of faulty blocks by spares when repairing the logic part of digital system-on-chip is proposed. The general provisions and rules of coverage for the matrix of configurable logic blocks (CLB) with faulty cells are considered. Coverage criteria for faulty cells are developed. Examples of the algorithm implementation are made. Billions of digital systems-on-chips, used in the world, containing up to 16 types of various components (processor, memory, logic, buses, dedicated computers), which can be divided into 2 subsets: the memory (90%) and logic (10%). At that faults, detected in memory, are repaired successfully by the onchip facilities of the leading companies (Virage Logic, Intel). But almost 10% of logic is unamenable to regular solutions in the on-chip repair. Today, the world's biggest problem in the market of electronic technology is repairing the logic part of digital system-on-chip. Due to high market appeal the problem of diagnosis and repair of memory and logic cells is considered in the paper. It is one of the Gartner's Top 10 Strategic Technologies for 2009 that is solved by readdressing faulty cells to faultless components from the spare rows, columns and tiles. The strategy works on the logic blocks, which must be addressed (and should be provided with repair blocks) or reprogrammable on the faultless space of the chip for the embedded repair. Repair models for SiP memory modules are considered in the papers [1-6]. It should also take into account that the level of sales of computers has fallen in the 2 quarter of 2009 by 8% and amounted to 66 million pieces, but sale of laptops has grown by 20%. With regard to market of chips, there is the highest rise of sales in the last 13 years. This fact confirms Moore's Law – transistor today is worthless, a user will pay for power. The whole world sees the future of digital systems-on-chips. Conclusion – all market-based ideas will be implemented in the chip with a dedicated functionality. So, Infrastructure IP creation in a chip is important problem, because it is capable to realize the embedded diagnosis and repairing, which will significantly improve the yield and extend the life cycle of digital product. Therefore, any new solution in this area might be interesting for the market of electronic technology, which determines the urgency of the proposed technology for quasi-optimal faulty blocks coverage by spare components. The papers [7-9] are devoted to the development of the theory and methods for optimization of geometric design, in particular, the research of optimization placement problem for rectangular objects. The optimization placement problem for rectangular objects with variable metric characterizations in a given area is considered in [7, 8]. The analysis of advanced technologies for embedded Functional Intellectual Property of digital system-in-package is shown in [10]. Features of the architecture «System-in-Package» and present repair strategies for digital systems-on-chips, as well as the method of evaluation the reliability of their performance are considered. The problem of SoC testing technologies adaptation to new digital system embodiment System-in-Package (SiP) that allows implementing on-chip sophisticated specialty computers and RF devices is considered in [10]. System-in-Package forms new objectives and goals of Infrastructure IP for real time SiP functionality, which differ from embedded SoC diagnosis essentially. Structure-logical diagnosis and repair methods for FPGA functional logic blocks based on real time fault detection table analysis are proposed. A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed in [10]. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The objective of the research is the development of technology for the optimal faulty blocks coverage by spares when repairing the logic of digital SoC. Research tasks are: 1) The development of generalities and rules to cover the matrix of configurable logic blocks with faulty cells. 2) The development of coverage criteria for faulty cells. 3) Flowcharting for the bypassing the matrix of configurable logic blocks to obtain coverage. 4) Flowchart examples.

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