Synchronizing sequences for verification of finite state machines

Публікація:
Synchronizing sequences for verification of finite state machines

dc.contributor.author	Shkil, O. S.
dc.contributor.author	Rakhlis, D. Y.
dc.contributor.author	Kulak, E. M.
dc.contributor.author	Miroshnyk, M. V.
dc.contributor.author	Pahomov, Y. V.
dc.contributor.author	Miroshnyk, A. M.
dc.date.accessioned	2020-06-04T16:47:13Z
dc.date.available	2020-06-04T16:47:13Z
dc.date.issued	2019
dc.description.abstract	Abstract—The method of detection and localization of design errors in HDL-models of finite state machines with arbitrary output functions was proposed. The diagnostic experiment is carried out bypassing all arcs of the Mealy machine, starting from the initial vertex, including for machines of the "non- exclusive" class. To ensure the return of the machine with a possible design error in the initial state, it is suggested to use synchronizing sequences. Diagnostic experiments were performed in the Active-HDL design environment.	uk_UA
dc.identifier.citation	Synchronizing sequences for verification of finite state machines / O. S. Shkil, D. Y. Rakhlis, E. M. Kulak and others, 2019, p.5	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/11986
dc.language.iso	en	uk_UA
dc.subject	verification	uk_UA
dc.subject	state machine	uk_UA
dc.subject	state diagram	uk_UA
dc.subject	diagnistic experiment	uk_UA
dc.subject	HDL	uk_UA
dc.subject	tests	uk_UA
dc.subject	waveform	uk_UA
dc.title	Synchronizing sequences for verification of finite state machines	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication