Diagnosis of SoC Memory Faulty Cells for Embedded Repair

Litvinova, E. I.; Hahanov, V. I.; Krasnoyaruzhskaya, K.; Galagan, S.

Публікація:
Diagnosis of SoC Memory Faulty Cells for Embedded Repair

dc.contributor.author	Litvinova, E. I.
dc.contributor.author	Hahanov, V. I.
dc.contributor.author	Krasnoyaruzhskaya, K.
dc.contributor.author	Galagan, S.
dc.date.accessioned	2016-09-02T06:19:24Z
dc.date.available	2016-09-02T06:19:24Z
dc.date.issued	2008
dc.description.abstract	A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It enables to obtain minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in the form of memory rows and columns. Modern digital systems-on-chip (SoC) include millions of equivalent gates and new high-level design technologies are necessary for their creation [1-3]. SoC memory in the future will occupy more than 90% of chip area that is oriented on use flexible software [3- 7,11]. Development of models and methods of quick and exact diagnosis, as well as technologies for repair of faulty cells by on-chip facility in real time and on all life cycle stages of a product are urgent problems. It will enable to decrease quantity of chip pins, to raise yield, to decrease time-to-market, to reduce service costs, as well as to remove output diagnosis and repair facility [1,6,7,12]. The research aim is development of algebra-logical method of embedded matrix memory diagnosis and repair in real time. The problems: 1) Analysis of SoC Infrastructure Intellectual Property Technologies; 2) Development of an Infrastructure Intellectual Property method on basis of the covering matrix; 3) Formalization of the algebralogical AL-method for embedded memory repair; 4) Analysis of obtained results. Modern design technologies of digital systems on chips propose along with creation of functional blocks F-IP development of service modules I-IP, which are oriented on complex solving of the project quality problem and yield increasing in manufacturing that is determined by implementation of the following services into a chip [11,14,16]: 1) Diagnosis of failures and faults by analysis of information, which is obtained on the stage of testing and use of special methods of embedded fault lookup on basis of the standard IEEE 1500 [8,13,15]; 2) Repair of functional modules and memory after fixation of a negative testing result, fault location and identification of a fault type in carrying out of the diagnosis phase; 3) Measurement of the general characteristics and parameters of a device operation on basis of on-chip facilities, which enable to make time and volt-ampere measurements; 4) Reliability and fault tolerance of a device operation in working that is obtained by diversification of functional blocks, redundancy of them and repair of SoC in real time.	uk_UA
dc.identifier.citation	Eugenia Litvinova Diagnosis of SoC Memory Faulty Cells for Embedded Repair /Vladimir Hahanov, Eugenia Litvinova, Karina Krasnoyaruzhskaya, Sergey Galagan //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1948
dc.language.iso	en	uk_UA
dc.publisher	EWDTS	uk_UA
dc.subject	SoC	uk_UA
dc.subject	Memory	uk_UA
dc.subject	Faulty cells	uk_UA
dc.subject	Embedded Repair	uk_UA
dc.title	Diagnosis of SoC Memory Faulty Cells for Embedded Repair	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication