Verification Challenges of Clock Domain Crossings

Abstract

This paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs.