Verification Challenges of Clock Domain Crossings

Публікація:
Verification Challenges of Clock Domain Crossings

dc.contributor.author	Zaychenko, S.
dc.contributor.author	Melnik, D.
dc.contributor.author	Lukashenko, O.
dc.date.accessioned	2016-09-06T09:05:49Z
dc.date.available	2016-09-06T09:05:49Z
dc.date.issued	2008
dc.description.abstract	This paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs.	uk_UA
dc.identifier.citation	Zaychenko S. Verification Challenges of Clock Domain Crossings/D. Melnik, S. Zaychenko, O. Lukashenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2135
dc.language.iso	en	uk_UA
dc.publisher	EWDTS	uk_UA
dc.subject	Verification	uk_UA
dc.subject	Clock Domain Crossings	uk_UA
dc.title	Verification Challenges of Clock Domain Crossings	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication