Verification of FPGA control systems by analyzing  the correctness of state diagrams

Публікація:
Verification of FPGA control systems by analyzing the correctness of state diagrams

dc.contributor.author	Shkil, O. S.
dc.contributor.author	Rakhlis, D. Y.
dc.contributor.author	Kulak, E. M.
dc.contributor.author	Filippenko, I. V.
dc.contributor.author	Miroshnyk, A. M.
dc.contributor.author	Miroshnyk, M. M.
dc.date.accessioned	2020-06-04T18:18:32Z
dc.date.available	2020-06-04T18:18:32Z
dc.date.issued	2020
dc.description.abstract	The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.	uk_UA
dc.identifier.citation	Verification of FPGA control systems by analyzing the correctness of state diagrams / Shkil O. S., Rakhkis D. Y., Kulak. E. M. // 2020. – 5 p.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/11993
dc.language.iso	en	uk_UA
dc.subject	finite state machine	uk_UA
dc.subject	state diagram	uk_UA
dc.subject	HDL-model	uk_UA
dc.subject	synthesis	uk_UA
dc.subject	orthogonal Boolean function	uk_UA
dc.title	Verification of FPGA control systems by analyzing the correctness of state diagrams	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication