Публікація: Transaction Level Model of Embedded Processor for Vector-Logical Analysis
Transaction level model of embedded processor for improving the performance of logical relation analysis are proposed. It is based on the hardware implementation of vector operations. There are examples of the model using for the semantics analysis of Russian adjectives. The embedded processor was designed to be part of SoC that will be implemented on FPGA. With the increase in complexity and velocity of the modern digital devices its energy consumption and cost gross also. The division of tasks across multiple cores of the processor that leads to create some parallel systems using a coherent set of specialized calculators would be a trade-off in this situation. These structures could improve the performance of solving the computational problems, and could reduce the power consumption and the hardware implementation cost of the digital systems. The special interest of electronic technology market is the scientific and technical direction of formalizing human mental activity to create the artificial intelligence components. These intelligent tools such as expert systems, image recognition and decisionmaking need creating effective and high-speed engines (multi-processor or specialized embedded processors). A typical example of this domain that requires a specialized processor is the analysis and synthesis of the natural language constructs. At the same time one of the main points of designing the word processor is the hardware implementation of the device that handle synthesis and analysis of the language constructs. Purpose: Development of the transaction level model of the special embedded processor for hardware realization of the vector operations. Objectives: 1. Analysis of publications about the specialized logic processor design [1-4]. 2. Analysis of the syntactic and semantic models of word processing that implement for natural languages [5-6]. 3. Creation of the architecture of the specialized embedded processor that analyze the logical net of the language constructs . 4. The hardware implementation of the transaction level model device that implements the grammatical analysis of the Russian adjectives. The prototype design is used the specialized device that performed grammatical analysis of adjectives end was implemented in the FPGA . The proposed model has more flexibility and can handle any logical net of syntactic and semantic relations. The use of the transaction level modes and design techniques allowed to focus on the order of the data processing and transmission, and reduce unimportant details.
Vector-Logical Analysis, Transaction Level Model, SoC, FPGA
Adamov Alexander Transaction Level Model of Embedded Processor for Vector-Logical Analysis/Irina V. Hahanova, Volodymyr Obrizan, Alexander Adamov, Dmitry Shcherbin//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2012)