Analysis of the state diagram correctness of automatic logic control systems on FPGA paper

Публікація:
Analysis of the state diagram correctness of automatic logic control systems on FPGA paper

dc.contributor.author	Shkil, O. S.
dc.contributor.author	Rakhlis, D. Y.
dc.contributor.author	Kulak, E. M.
dc.contributor.author	Filippenko, I. V.
dc.contributor.author	Miroshnyk, M. M.
dc.contributor.author	Hoha, M. V.
dc.date.accessioned	2020-06-04T18:20:53Z
dc.date.available	2020-06-04T18:20:53Z
dc.date.issued	2019
dc.description.abstract	The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.	uk_UA
dc.identifier.citation	Analysis of the state diagram correctness of automatic logic control systems on FPGA paper / O. S. Shkil, D. Y. Rakhlis, E. M. Kulak and others / Metrology and metrology assurance 2019. – Sopozol, Bulgaria, 2019. – p.16	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/11995
dc.language.iso	en	uk_UA
dc.subject	HDL-model	uk_UA
dc.subject	state machine	uk_UA
dc.subject	state diagram	uk_UA
dc.subject	decision-making	uk_UA
dc.subject	orthogonal Boolean function	uk_UA
dc.title	Analysis of the state diagram correctness of automatic logic control systems on FPGA paper	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication