Testable design of control digital automatic machines

Shkil, O. S.; Rakhlis, D. Y.; Kulak, E. M.; Filippenko, I. V.; Miroshnyk, M. M.

Публікація:
Testable design of control digital automatic machines

dc.contributor.author	Shkil, O. S.
dc.contributor.author	Rakhlis, D. Y.
dc.contributor.author	Kulak, E. M.
dc.contributor.author	Filippenko, I. V.
dc.contributor.author	Miroshnyk, M. M.
dc.date.accessioned	2020-06-04T16:46:30Z
dc.date.available	2020-06-04T16:46:30Z
dc.date.issued	2020
dc.description.abstract	Abstract—The aim of the work is to analyze hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM’s states depending on the presence of an unconditional transition, a conditional transition, and the absence of transitions between states of analyzed FSM. The conclusion on additional hardware costs is made on the basis of a comparison of synthesis results of testable HDL-models by means of CAD FPGA. The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state. The best way to organize additional transitions during setting of control FSM in an arbitrary state is the transition for which the total hardware cost estimate for the excitation functions is minimal, taking into account the coding of FSM’s states.	uk_UA
dc.identifier.citation	Testable design of control digital automatic machines / O. S. Shkil, D. Y. Rakhlis, E. M. Kulak and others. – 2020, p.6.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/11985
dc.language.iso	en	uk_UA
dc.subject	hardware costs	uk_UA
dc.subject	design for testability	uk_UA
dc.subject	control FSM	uk_UA
dc.subject	transition-output table	uk_UA
dc.subject	hardware description language	uk_UA
dc.subject	automated synthesis	uk_UA
dc.title	Testable design of control digital automatic machines	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication