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Публікація Assertions based verification for systemc(EWDTW, 2005) Forczek, M.; Zaychenko, S.The Assertions Based Verification (ABV) has gained worldwide acceptance as verification methodology of electronic systems designs. There was number of papers [1-3] that explain in-depth this methodology. The original concept of assertion comes from software development where it (in particular the assert() macro defined in C language [4]) has proved to be a very powerful tool for automatic bug and regression detection [5]. Assertions for hardware designs employ Linear Time Logic (LTL) to define expected and/or forbidden behavior. The foundation for ABV are Hardware Verification Languages (HVLs). HVLs combine semantics of LTL with constructs for building reusable verification IP units. Verification IP units need to be bind to some design for effective use. Thus HVLs provide constructs to specify connections with models in Hardware Description Languages (HDLs). Most of ABV implementations are part of HDL–based integrated design environments (IDEs). The SystemC open initiative [6] provides an alternative to HDLs as it enables C++ [7] – the industry strength notation for complex systems – with hardware concepts of RTL and system-level in form of C++ templates library. In its original approach SystemC models are processed standard C++ toolset and executed as standalone applications. SystemC became a very popular environment for modeling at system-level abstraction. The HDL-based IDEs offer co-simulation capabilities with SystemC engine but it still remain external unit to the HDL simulator. The idea of applying ABV to the SystemC designs is natural step of HDL and SystemC environments integration. Since HDL design can be co-simulated with SystemC model, there is an easy way to associate verification unit with SystemC one: the SystemC unit needs to be connected to HDL wrapper unit that will provide entry point for verification unit bind. This method doesn’t require any additional tools assuming availability of HDL simulator.Публікація Assertions-based mechanism for the functional verification of the digital designs(EWDTW, 2005) Hahanov, V. I.; Yegorov, O.; Zaychenko, S.; Parfentiy, A.; Kaminska, M.; Kiyaschenko, A. V.According to [1] the verification cost of the digital devices, designed on the base of ASIC, IP-core, SoC technologies, takes up to 70% of the overall design cost. Similarly, up to 80% of the project source code implements a testbench. Reducing these two mentioned parameters minimizes timeto-market, and this is one of the main problems for the world-leading companies in the area of Electronic Design Automation (EDA). The goal of the verification tasks is to eliminate all design errors as early as possible to meet the requirements of the specification. Passing the error through the subsequent design stages (from a block to a chip, and later to a system) each time increases the cost of it’s elimination. Validation – a higher-level verification model – confirms the correctness of the project against the problems in the implementation of the major specified functionality. The goal of this paper is to noticeably decrease the verification time by extending the design with software-based redundancy – the assertions mechanism [2-5], which allows to simply analyze the major specified constraints during the device simulation process and to diagnose the errors in case of their detection. To achieve the declared goal it is necessary to solve the following problems: 1. To formalize the assertions-based product verification process model. 2. To develop the software components for synthesis and analysis of the assertions for the functionality, blocks and the entire system. 3. To get experimental confirmation of the benefits from using assertions to reduce time-to-market or, in other words, to noticeably reduce verification and overall design time.Публікація Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints(EWDTW, 2006) Zaychenko, S.; Hahanov, V.; Zaharchenko, O.Today the Assertions Based Verification (ABV) is by all means the most effective verification technology for SoC designs. Assertions provide basic blocks for building functional verification concept. Assertions simply catch a lot of design errors on early phases. This paper suggests new effective algorithmic model for assertions checking within the testbench-based simulation. The algorithms for handling key temporal operators from Property Specification Language (PSL) are described. Paper demonstrates the advantages of the suggested model over existing equivalents - in simulation performance, verification efficiency and model extensibility. Obviously, the verification process is a very complex and a very expensive part of the modern SoC design cycle. This process consists of searching the model for mistakes, causing the design to violate the functional specification, localizing the problems reasons and applying the fixtures. According to the EDA industry experts opinion, the cost of verification in ASIC [1] designs often overheads the 70% of the entire project budget [2]. Such high cost of the system quality is driven by several factors, in particular: – A large amount of missed details and mistakes in the work of SoC designers in the RTL code, verification engineers mistakes in the testbenches, also, the inevitable ambiguities of the original design specification; – drawbacks in the choosen design flows, complicating the bugs localization and fixtures, missing the possibilities for early discovery of the typical problems; – relatively low performance and bugs within the selected automation tools, which reach the quality and performance goals much slower than the input design complexity raises. Resolving these problems altogether and degrading the SoC verification cycle cost is currently a primary goal for the entire EDA world [3]. Leading EDA companies and industry experts are focused on developing the new generation of complex design verification methods, which will be able to: – minimize the human participation in the routine design and verification procedures, which will obviously decrease the probability of mistakes in several times; – lead to catching the largest amount of problems on the early design phases, reducing the average fixture cost; – upgrade the performance and stability of the design verification systems by raising the abstraction level both for the SoC models and for the testing stimulus. There are two basic directions in modern SoC verification methods – dynamic methods [2,4], based on the simulation, and static, or formal methods [5,6], based on the mathematical proof of certain system properties without testing stimulus. There are also hybrid methods [7] used, which assume usage of the simulation and functional coverage results to improve the performance of formal methods. This work is focused on the assertions-based verification technology [8,9], playing its role both in dynamic and formal methods.Публікація Early Detection of Potentially Non-synchronized CDC Paths Using Structural Snalysis Technique(EWDTS, 2009) Zaychenko, S.; Melnik, D.; Lukashenko, O.The number of independent clock domains found on the typical today's device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >15-20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today's SoC design methodology; only static techniques can work as soon as the RTL starts taking shape. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis. The sections of logic elements that driven by clocks coming from different sources are called clock domains. The signals that interface between asynchronous clock domains are called the clock domain crossing (CDC) signals. The DATA_A signal is considered as an asynchronous signal into the receiving clock domain (no constant phase and time relationship exists between CLK_A and CLK_B).The nature of CDC bugs is intermittent; it simply means that a test suite can be successfully completed on a chip in the morning, but the same tests will complete with errors for the same chip in the afternoon. Consider the simplest flip-flop example: such a flip-flop is located anywhere in the chip; the data signal for this flip-flop comes from the domain #A but the clock signal — from the domain #B... so whenever the setup or hold condition is violated, the flip-flop can go to one or to zero and it cannot be predicted.Публікація Method for Diagnosing SoC HDL-code(EWDTS, 2014) Zaychenko, S.; Hahanov, V.; Varchenko, V.This article describes technology for diagnosis SoC HDL-models, based on Code-Flow Transaction Graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis. The goal is creation TAB-matrix model (Tests – Assertions – Blocks functional) model and diagnosis method to decrease the time of testing and memory for storage by means of forming ternary relations (test – monitor – functional component) in a single table. The problems are: 1) development of digital system HDL-model in the form of a transaction graph for diagnosing functional blocks by using assertion set; 2) development method for analyzing TABmatrix to detect minimal set of fault blocks; 3) Synthesis of logic functions for embedded fault diagnosis procedure.Публікація System Level Methodology for Functional Verification Soc(EWDTW, 2006) Adamov, A.; Zaychenko, S.; Myroshnychenko, Y.; Lukashenko, O.Building a verification environment and the associated tests is a highly time-consuming process. Most project reports indicate that between 40% and 70% of the entire effort of a project is spent on verification, with 70% being much closer to the normal level for successful projects. This high level of effort indicates that the potential gains to be made with successful re-use are significant. Most projects do not start with a complete set of hardware designs available for a functional verification. Usually a design comes together as smaller blocks. Then the blocks are integrated into larger blocks, which may eventually be integrated into a system. That is reason for performing functional verification at a system level. The paper describes the system-level modeling environment for a functional verification System-on-a-Chip models. System level allow design teams to rapidly create large system-on-a-chip designs (SOCs) by integrating premade blocks that do not require any design work or verification. One of the hottest topics in embedded system design today is Electronic System Level (ESL) design. Although the idea of being able to describe a system at an abstract level has been around for a decade, only now are various parts of the design flow becoming available to make it practical. ESL describes a Systemon- chip (SoC) design in an abstract enough and fast enough way to explore the design space and provide virtual prototypes for hardware and software implementation. It is becoming a fundamental part of the design flow because we can now use it throughout the iterative design process rather than just in the early system architecting phase. ESL provides tools and methodologies that let designers describe and analyze chips on a high level of abstraction, easing the pain of designing electronic systems which would otherwise be too costly, complex or time consuming to create. The adoption of ESL can be seen in the same light as the transition to register transfer level (RTL) methodologies 10-15 years ago when complexity and time-to-market pressures obliged the industry to step up to another design level. As designs become larger with more and more IP blocks, engineers will re-use more IP. ESL methodologies that enable platform-based design will be increasingly necessary to create and test a complete system. For the most complex SoCs, IP reuse can only help up to a point. For a 40-million-gate SoC, filling even 75% of the device with existing IP leaves 10 million gates to design with original content. ESL methodologies which allow rapid creation of new blocks are likely to be leveraged by designers to quickly develop and verify original content to fill the 10 million gate void while meeting time-to- market requirements. Among the 24% percent of respondents who have implemented some form of ESL design methodology an overwhelming 87% believe ESL provides an acceptable or greater return on investment.Публікація Verification Challenges of Clock Domain Crossings(EWDTS, 2008) Zaychenko, S.; Melnik, D.; Lukashenko, O.This paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs.