Перегляд за автором "Titarenko, L."

Зараз показано 1 - 4 з 4
  • Зображення мініатюри
    Публікація
    Encoding of Terms in EMB-Based Mealy FSMs
    (ХНУРЕ, 2020) Barkalov, A. A.; Titarenko, L.; Mazurkiewicz, M.; Krzywicki, K.
    AmethodisproposedtargetingimplementationofFPGA-basedMealyfinitestatemachines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levelsinFSMlogiccircuits. Todoit,itisnecessarytoeliminatethedirectdependenceofinputmemory functions and FSM output functions on FSM inputs and state variables. The method is based on encodingofthetermscorrespondingtorowsofdirectstructuretables. Insuchanapproach,onlyterms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.
  • Зображення мініатюри
    Публікація
    FPGA-based implementing fsm for emc
    (ХНУРЕ, 2019) Titarenko, L.; Barkalov, A. A.
    The method of synthesis and implementation into FPGAs of Mealy FSMs is proposed. Synthesis is based on structural decomposition of initial circuit. FSM states are divided by classes and encoded separately in each class. The states are decoded in the second-level circuit. It leads to implementation of FSM in double-level structure where utilization of both, LUTs and embedded memory blocks, is applied. It leads to balanced usage of hardware resources of an FPGA de-vice. The method targets blocks for electromagnetic compatibility of radiotechnical devices.
  • Зображення мініатюри
    Публікація
    Matrix Implementation of Moore FSM with Encoding of Collections of Microoperations
    (ХНУРЭ, 2009) Barkalov, A. A.; Titarenko, L.; Hebda, O. P.; Soldatov, K.
    The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The method is oriented on customized matrix technology. It is based on representation of the next state code as a concatenation of code for class of collection of microoperations and code of the vertex. Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given.
  • Зображення мініатюри
    Публікація
    State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States
    (ХНУРЭ, 2008) Bukowiec, A.; Barkalov, A. A.; Titarenko, L.
    The method of synthesis and implementation into FPGAs (Field Programmable Gate Arrays) of Mealy FSMs (Finite State Machines) is proposed. Synthesis is based on the architectural decomposition and the multiple encoding. A set of states is divided into subsets based on a current state or a executed microinstruction. Then, states are encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state or the code of a executed microinstruction. It leads to implementation of an FSM in double-level structure where utilization of both, LUTs (Look-Up Tables) and embedded memory blocks, is applied. It leads to balanced usage of hardware resources of an FPGA device.