Перегляд за автором "Kaminska, M."

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  • Зображення мініатюри
    Публікація
    Assertions-based mechanism for the functional verification of the digital designs
    (EWDTW, 2005) Hahanov, V. I.; Yegorov, O.; Zaychenko, S.; Parfentiy, A.; Kaminska, M.; Kiyaschenko, A. V.
    According to [1] the verification cost of the digital devices, designed on the base of ASIC, IP-core, SoC technologies, takes up to 70% of the overall design cost. Similarly, up to 80% of the project source code implements a testbench. Reducing these two mentioned parameters minimizes timeto-market, and this is one of the main problems for the world-leading companies in the area of Electronic Design Automation (EDA). The goal of the verification tasks is to eliminate all design errors as early as possible to meet the requirements of the specification. Passing the error through the subsequent design stages (from a block to a chip, and later to a system) each time increases the cost of it’s elimination. Validation – a higher-level verification model – confirms the correctness of the project against the problems in the implementation of the major specified functionality. The goal of this paper is to noticeably decrease the verification time by extending the design with software-based redundancy – the assertions mechanism [2-5], which allows to simply analyze the major specified constraints during the device simulation process and to diagnose the errors in case of their detection. To achieve the declared goal it is necessary to solve the following problems: 1. To formalize the assertions-based product verification process model. 2. To develop the software components for synthesis and analysis of the assertions for the functionality, blocks and the entire system. 3. To get experimental confirmation of the benefits from using assertions to reduce time-to-market or, in other words, to noticeably reduce verification and overall design time.
  • Зображення мініатюри
    Публікація
    Hierarchical Analysis of Testability for SoCs
    (EWDTW, 2006) Kaminska, M.; Hahanov, V. I.; Kulak, E.; Guz, O. A.
    This paper presents the strategy of testable SoC design procedure. This approach based on the testability analysis on different levels of abstractions (gate level, register transfer level, system level). Analysis is based on structural analysis of SoC. Proposed methods give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The main goal of the presented algorithms is to increase fault coverage before test generation and to decrease verification time. It could be reached by improving of testability and simplification of the verification task. As a complexity of today’s ASIC designs continues to increase, the challenge of verifying these designs intensifies at an even greater rate [1]. Testability is one of the most important factors that are considered at digital devices design along with reliability, speed and the cost. The low level of device testability leads to increasing of number of non-tested faults and verification time at design, production and operations stages. Therefore, the cost of diagnostic (a degree of faults concentration) decreases essentially during techniques of testability design. The cost of a fault essentially increases in the process of ASIC crystal implementation (Fig. 1). Hence analysis of testability needs to be done at earlier level of device description. This is the main reason of development of the methods of testability analysis at the different levels of abstraction: system, RT, and gate levels. Object under test – system on chip, which can be presented on different levels of abstraction. Goal of work – maximal decreasing of test procedure cost; to provide digital circuit testability on all design levels of abstraction, till device manufacturing stage. To provide device testing possibility with minimal test by adding of scan cells on bottlenecks in circuit (circuit’s parts, which hard to test).