Перегляд за автором "Guz, O. A."
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Публікація Algebra-Logical Repair Method for FPGA Logic Blocks(ХНУРЭ, 2009) Hahanov, V. I.; Gharibi, W.; Guz, O. A.; Litvinova, E. I.An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the operability of FPGA blocks and digital system as a whole. It enables to obtain exact and optimal solution associated with the minimum number of spares needed to repair the FPGA logic components with multiple faults.Публікація Cloud Traffic Control System(EWDTS, 2013) Ziarmand, A.; Hahanov, V. I.; Guz, O. A.; Ngene, C. U.; Arefjev, A.A cloud service “Green Wave” (the intellectual road infrastructure) is proposed to monitor and control traffic in real-time through the use of traffic controllers, RFID cars, in order to improve the quality and safety of vehicle movement, as well as for minimization the time and costs when vehicles are moved at the specified routes. The evolution of cyber world is divided into the following periods: 1) the 1980s - formation of personal computers; 2) the 1990s - the introduction of Internet technologies in production processes and people's lives; 3) the 2000s - improving the quality of life through the introduction of mobile devices and cloud services, and 4) the 2010s - the creation of a digital infrastructure for monitoring and control of moving objects (air, sea, ground transportation, and robots). Therefore, in the present market feasible problem is the system integration of monitoring-control cloud service and transport RFID blocks as well as digital tools of road infrastructure for optimal on-line vehicle and traffic control in order to address the social, human, economic and environmental problems. What is the basic of the world cyberspace? – The silicon chip and its analogs. Modern microelectronics enables to create not flat but three-dimensional transistor structures (3D – FinFETs) in 14 nm range, commensurate with the size of the atom. This means the appearance in the near future 3D-System-on-Chip instead of flat structures or system-in-package. The advantages of the chips significantly affect the characteristics of industrial products in terms of: energy consumption, dimensions, performance, cost and quality due to reducing not only the dimension of the components, but also the relationships between them. Thus there arise problems associated with heat removal from the internal area of 3D-chip, as well as the creation of new technologies for designing, verification, testing, diagnosis and repairing of its components. Thus, a microworld of cyberspace goes in 3Dmeasurement not easily. Macroworld remains flat when components, computers, networks, cloud services of cyberspace are combined into the system. Which arguments could be made for the transfer of the macroworld in 3D-space? They are the following: the compactness of information, the performance of searching in cyberspace, and its dimension. The triangular flat structure of the system where all nodes are adjacent has a major drawback in the two dimensions – for encoding three nodes or edges it is necessary three codes, and this means that one code of two-bit vector is not used. Therefore, the creation of a primitive structure, where all nodes are adjacent and their number is four to make full use of the two bits code space, means re-open an amazing 3D-figure - a tetrahedron! It has six edges or distances, xor-sum of which is equal to zero. When descripting the figure two edges are redundant, which can be used to reduce the volume of information up to 66% during storage and transfer of data. Formation of cyberspace through the use of primitive tetrahedra allows optimizing (minimizing) the ratio of the structural complexity of the space to the average distance between two points. Object of research is technologies for monitoring and management of vehicles integrated with cloud services, based on the use of the existing road infrastructure, RFID, radar and radio navigation. Subject of research: traffic and road infrastructure of Ukraine and its regions, as well as advanced software and hardware RFID systems for monitoring and road management, based on the use of road controllers, global systems for positioning, navigation (GPS, GPRS), and cloud services in the Internet. The essence of research is creation of intellectual road infrastructure (IRI) – cloud service "Green Wave" for monitoring infrastructure and management of road in real-time, based on creating virtual road infrastructure (Fig. 2), integrated with road traffic controllers, RFID of vehicles in order to improve the quality and safety of vehicle movement, minimization of time and costs when realization of routes.Публікація Co-design technology of soc based on active-HDL 6.2(EWDTW, 2004) Hyduke, S.; Yegorov, A. A.; Guz, O. A.; Hahanova, I. V.It is represented technology of designing and verification of digital systems-on-a-chip (SoC), based on the experience of design of hardware and software components of SoC in one environment. It reflects today situation of variety of available silicon, software and hardware description languages, design tools. There are also presented recommendations and examples. On today’s EDA market there are 3 major target silicon technologies that define computer world today – programmable devices, gate arrays and ASICs. They and relations between them are presented on Fig. 1. That includes manufacturing technology of silicon chips, hardware and software description languages, design tools, SoC methodology. ASIC GA PLD ASIC + PLD CPU+PLD ASIC+CPU+PLD 90 Nm-technology ASIC +CPU Design tools based on HDL SOCs based on: Fig. 1. Cause-effect relation on the EDA market Practical explanation of presented figure is that because of influence of SoC on ASIC and FPGA (PLD) designs it is started integration between them. On FPGA’s started to appear powerful embedded processors such as ARM and PowerPC. For example latest Xilinx Virtex II Pro FPGA is 4 embedded IBM PowerPC processors plus 10 million of programmable gates available for user. Design flows of FPGAs and ASICS also started to merge after announcing by Altera Structured ASIC flow. Where FPGA verified design is transferred to ASIC without any participation of the developer. That will influence world chip market – that is about $40 billions per year: 1) powerful processors, that are used on servers and working stations; 2) personal computers area, where Intel processors holding the leading place with $20 billions; 3) microcontrollers and signal processes generate to vendors $14 billion revenue every year. The 3rd segment is the most growing one from all three. Hardware development reached stage that number of transistors is growth is 60% per year, but their usage in project growing only 20% per year. That’s why we can see today rapid growth of number of SoCs. On that available space on a chip are transferred from the board all buses and peripherals of the developed system. That allows not only increasing productivity of whole digital system and make it with custom functionality, but significantly to reduce energy consumption and decrease physical size of final product. At the same time one of the main requirements of designing complex systems today is to use module approach. Where designer can reuse modules from previous projects or use IP(Intellectual Property)-core. For SoCs there are bunch of various ready to use processors with peripheral buses and libraries of standard peripherals. With different functionality, sizes, from simple interface to complicated 64bit processors that requires couple of millions transistors.Публікація Coverage Method for FPGA Fault Logic Blocks by Spares(EWDTS, 2009) Hahanov, V. I.; Litvinova, E. I.; Gharibi, W.; Guz, O. A.A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The problem of testing technologies adaptation for new digital system-in-package (SiP), which gradually develops the market of electronic technology [1-6] is considered. SiP forms new challenges of real-time Infrastructure IP for system functionalities, which differs from embedded diagnosis of SoC components essentially. Yervant Zorian is leading scientist in the field of Design and Test in the world [3] and he said now the main problem of digital system repairing is designing the methods and technologies for on-chip logic repairing although it occupies no more 10% of chip area. Objective of the research is design of a method for on-chip diagnosis of digital system-on-a-chip on the basis of traversal the rows and columns to increase SiP testability, quality and reliability. The problems are: 1) design of a matrix model for the FPGA logic blocks in the form of tiles, which contain faults; 2) design of a coverage method for faulty logic blocks by spare tiles in the traversal of matrix rows or columns; 3) testing and verification of the method on examples of logic block matrixes, containing various faulty configurations.Публікація Hierarchical Analysis of Testability for SoCs(EWDTW, 2006) Kaminska, M.; Hahanov, V. I.; Kulak, E.; Guz, O. A.This paper presents the strategy of testable SoC design procedure. This approach based on the testability analysis on different levels of abstractions (gate level, register transfer level, system level). Analysis is based on structural analysis of SoC. Proposed methods give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The main goal of the presented algorithms is to increase fault coverage before test generation and to decrease verification time. It could be reached by improving of testability and simplification of the verification task. As a complexity of today’s ASIC designs continues to increase, the challenge of verifying these designs intensifies at an even greater rate [1]. Testability is one of the most important factors that are considered at digital devices design along with reliability, speed and the cost. The low level of device testability leads to increasing of number of non-tested faults and verification time at design, production and operations stages. Therefore, the cost of diagnostic (a degree of faults concentration) decreases essentially during techniques of testability design. The cost of a fault essentially increases in the process of ASIC crystal implementation (Fig. 1). Hence analysis of testability needs to be done at earlier level of device description. This is the main reason of development of the methods of testability analysis at the different levels of abstraction: system, RT, and gate levels. Object under test – system on chip, which can be presented on different levels of abstraction. Goal of work – maximal decreasing of test procedure cost; to provide digital circuit testability on all design levels of abstraction, till device manufacturing stage. To provide device testing possibility with minimal test by adding of scan cells on bottlenecks in circuit (circuit’s parts, which hard to test).Публікація Hierarchical hybrid approach to complex digital systems testing(EWDTW, 2005) Hahanova, I. V.; Obrizan, V.; Ghribi, W.; Yeliseev, V.; Ktiaman, H.; Guz, O. A.This paper offers approach to complex digital system testing based on hierarchy scaling during diagnosis experiment. Several models of testing are proposed. Main principles of testing system organization are given. Such approach allows significant reducing overall system testing and verification time.Публікація Synthesis of Qubit Models for Logic Circuits(EWDTS, 2012) Zaychenko, S. A.; Gharibi, W.; Dahiri Farid; Hahanova, Yu. V.; Guz, O. A.; Ngene, C. U.; Adiele StanleyQubit (quantum) structures of data and computational processes for significantly improving performance when solving problems of discrete optimization and fault-tolerant design are proposed. We describe superpositional method for synthesizing cube of functionality for its implementation in the structural components of programmable logic chips. The estimates of synthesis time, as well as hardware costs for creating qubit models of logic circuits are represented. Quantum computing becomes interesting for cyberspace analysis, creating new Internet technologies and services, which is explained by their alternative to the existing models of computing processes. Market appeal of quantum (qubit) models is based on the high parallelism when solving almost all discrete optimization problems, factoring, minimization of Boolean functions, effective compression of data, their compact representation and teleportation, fault-tolerant design through significant increase in hardware cost. But now it is acceptable, because there are problems of use silicon chip, which contains up to 1 billion gates on a substrate thickness 5 microns. At that modern technologies allow creating a package (sandwich) containing up to 7 chips, which is comparable with the quantity of the human brain neurons. Practically, through-silicon via (TSV) connection is based on the technological capability of drilling about 10 thousand through vias in 1 square centimeter of wafer or die. Layout the indicated volume of useful functionality on chip is currently problematic. So, it is necessary to develop hardwarefocused models and methods for creating high-speed tools of parallel solving real world problems. Considering the discreteness and multiple-valuedness of the alphabets for description of information processes, the parallelism, inherent in the quantum computing, is particularly actual when developing effective and intelligent engines for cyberspace or Internet, tools for synthesis of fault-tolerant digital primitives and systems, testing and simulation of digital systems-on-chips, technologies for information and computer security, brain-like models for computing, analysis and synthesis of linguistic constructions.Публікація Vector-Logical Diagnosis Method for SOC Functionalities(EWDTS, 2008) Hahanov, V. I.; Guz, O. A.; Kulbakova, N.; Davydov, M.Models and methods of vector-logical diagnosis of SoC functionalities in real time are proposed. Algebralogical procedures of embedded fault diagnosis by means of DNF synthesis that forms all functionality diagnosis solutions are described. The method is based on use the fault detection table that is result of fault simulation. The research aim is development of embedded diagnostic service method of digital system-on-a-chip functionalities that is intended for faulty SoC component detection in real time. The problems: 1) The state of the SoC I-IP market technology [1-5]; 2) Vector-logical (VL) method of the embedded service on basis of the coverage matrix [6,7]; 3) VL-method application for the diagnosis of SoC components; 4) Practical results of the investigations. Modern technologies for the design of digital systems on chip [8-11] offer, along with the functional blocks of F-IP, the development of service modules IIP oriented on the integrated solution of the problem of improving the project quality and Yield increasing in the manufacturing process, which is defined by implementation to silicon the following services [2,4,5]: 1) Monitoring the internal and output lines in the operation, verification and testing of functional blocks on the basis of IEEE 1500 boundary scan standard [12]; 2) Testing the functional modules by applying different test generators, targeting fault detection or behaviour checking; 3) Diagnosis failures and defects by analyzing the information received from testing phase and by using the special embedded methods for troubleshooting based on the IEEE 1500 standard [12]; 4) Repair of functional modules and memory after fixing a negative test result and determination the type and location of a defect at the executing diagnosis phase; 5) Built-in-measurement the main parameters and characteristics of SoC operation, allowing the temporal and volt-ampere measurements; 6) The reliability and fault tolerance of SoC in the operation, which are achieved by using diversification of functional blocks, duplication of them and recovery SoC efficiency in real time. Subject to the SoC testing problem’s state the fault diagnosis problem is considered below, defined by item 3; its solving enables to raise the quality of designed device essentially due to technological method of a single and multiple faults detection.Публікація Verification and Diagnosis of SoC HDL-code(EWDTS, 2011) Hahanov, V. I.; Park, Dong Won; Guz, O. A.; Galagan, S.; Priymak, A.Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertionbased models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered. Recent trends in creating new communications, computing and information services, useful to the human, are development of dedicated gadgets, which have important advantages over PCs and laptops: power consumption, compactness, weight, cost, functionality, and friendliness of interface. Practically the top ten dedicated products 2010 (Apple iPad, Samsung Galaxy S, Apple MacBook Air, Logitech Revue, Google Nexus One (HTC Desire), Apple iPhone 4, Apple TV, Toshiba Libretto W100, Microsoft Kinect, Nook Color) is realized as digital systems-on-chips. By 2012 the mobile and wireless communication market will move to 20 nm (results of the January 2011 Technology Forum of Common Platform Alliance). Further development of the technologies by year: 2014 – 14 nm, 2016 – 11 nm. In 2015 more than 55% of mobile phones will be smartphones, tablet PCs will replace laptops and netbooks. Superfones (Nexus-1, Google) will unite all devices and services. The transition from the computing platform to mobile devices with small size results in considerable reduction in power consumption worldwide. The next computerization wave, entitled "Internet of things", is being accelerated. It will lead to widespread sensor networks, including their integration into the human body. The world market of the above devices and gadgets today involves about 3 billion products. For their effective designing, manufacturing and exploitation the new technologies and Infrastructures IP are created.