Радиоэлектроника и информатика
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Перегляд Радиоэлектроника и информатика за автором "Barkalov, A. A."
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Публікація Matrix Implementation of Moore FSM with Encoding of Collections of Microoperations(ХНУРЭ, 2009) Barkalov, A. A.; Titarenko, L.; Hebda, O. P.; Soldatov, K.The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The method is oriented on customized matrix technology. It is based on representation of the next state code as a concatenation of code for class of collection of microoperations and code of the vertex. Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given.Публікація Modification of Elementary Operational Linear Chains in Compositional Control Unit with Code Sharing(ХНУРЭ, 2008) Barkalov, A. A.; Titarenko, L. A.; Miroshkin, A. N.The new design method for compositional microprogram control units with code sharing and elementarization of operational linear chains is proposed. The method targets on reduction in the number of LUT-elements in the combinational part of control unit. Some additional control microinstructions containing codes of the classes of pseudoequivalent chains are used for operational linear chains modification. Proposed method is illustrated by an example. Most desirable GSA characteristics for using proposed method were obtained.Публікація Optimization of Control Unit with Code Sharing(ХНУРЭ, 2009) Barkalov, A. A.; Titarenko, L. A.; Miroshkin, A. N.The new design method for compositional microprogram control units with code sharing is proposed. The method targets on reduction in the number of PAL macrocells in the combinational part of control unit. Some additional control microinstructions containing codes of the classes of pseudoequivalent chains are used for operational linear chains modification. Proposed method is illustrated by an example. Various graph-scheme of algorithm (GSA) research results are illustrated with the diagrams. Most desirable GSA characteristics for using proposed method were obtained.Публікація Reduction of Hardware Amount for Control Unit with Address Transformer(ХНУРЭ, 2009) Barkalov, A. A.; Titarenko, L. A.; Lavrik, A. S.The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given.Публікація State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States(ХНУРЭ, 2008) Bukowiec, A.; Barkalov, A. A.; Titarenko, L.The method of synthesis and implementation into FPGAs (Field Programmable Gate Arrays) of Mealy FSMs (Finite State Machines) is proposed. Synthesis is based on the architectural decomposition and the multiple encoding. A set of states is divided into subsets based on a current state or a executed microinstruction. Then, states are encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state or the code of a executed microinstruction. It leads to implementation of an FSM in double-level structure where utilization of both, LUTs (Look-Up Tables) and embedded memory blocks, is applied. It leads to balanced usage of hardware resources of an FPGA device.