State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States

Abstract

The method of synthesis and implementation into FPGAs (Field Programmable Gate Arrays) of Mealy FSMs (Finite State Machines) is proposed. Synthesis is based on the architectural decomposition and the multiple encoding. A set of states is divided into subsets based on a current state or a executed microinstruction. Then, states are encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state or the code of a executed microinstruction. It leads to implementation of an FSM in double-level structure where utilization of both, LUTs (Look-Up Tables) and embedded memory blocks, is applied. It leads to balanced usage of hardware resources of an FPGA device.