State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States

Bukowiec, A.; Barkalov, A. A.; Titarenko, L.

Публікація:
State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States

dc.contributor.author	Bukowiec, A.
dc.contributor.author	Barkalov, A. A.
dc.contributor.author	Titarenko, L.
dc.date.accessioned	2016-08-25T06:14:18Z
dc.date.available	2016-08-25T06:14:18Z
dc.date.issued	2008
dc.description.abstract	The method of synthesis and implementation into FPGAs (Field Programmable Gate Arrays) of Mealy FSMs (Finite State Machines) is proposed. Synthesis is based on the architectural decomposition and the multiple encoding. A set of states is divided into subsets based on a current state or a executed microinstruction. Then, states are encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state or the code of a executed microinstruction. It leads to implementation of an FSM in double-level structure where utilization of both, LUTs (Look-Up Tables) and embedded memory blocks, is applied. It leads to balanced usage of hardware resources of an FPGA device.	uk_UA
dc.identifier.citation	Bukowiec, A. State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States / A. Bukowiec, A. Barkalov, L. Titarenko // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 4. – С. 43-48.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1846
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	circuit synthesis	uk_UA
dc.subject	field programmable gate arrays	uk_UA
dc.subject	finite state machines	uk_UA
dc.subject	logic design	uk_UA
dc.title	State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication