A Method of High-Level Synthesis and Verification with SystemC Language

Публікація:
A Method of High-Level Synthesis and Verification with SystemC Language

dc.contributor.author	Obrizan, V.
dc.date.accessioned	2016-09-06T07:28:09Z
dc.date.available	2016-09-06T07:28:09Z
dc.date.issued	2010
dc.description.abstract	This paper presents a method for automatic RTL-interface synthesis for a given C++ function as well as for a given SystemC-interface. This task is very im-portant in High-Level Synthesis design flow where design entry is usually done in some abstract language (e.g. C++). As a source high-level description targets different SoC architectures or protocols, so it is needed to generate relevant pin-level interfaces and protocols automatically.	uk_UA
dc.identifier.citation	Obrizan, V. A Method of High-Level Synthesis and Verification with SystemC Language / V. Obrizan // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 47-50.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2125
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	system testing	uk_UA
dc.subject	system-level design	uk_UA
dc.subject	high level synthesis	uk_UA
dc.subject	computer languages	uk_UA
dc.title	A Method of High-Level Synthesis and Verification with SystemC Language	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication