Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

Arabian, J. H.

Публікація:
Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

dc.contributor.author	Arabian, J. H.
dc.date.accessioned	2016-09-01T10:35:22Z
dc.date.available	2016-09-01T10:35:22Z
dc.date.issued	2009
dc.description.abstract	TESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.	uk_UA
dc.identifier.citation	Arabian, J. H. Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation / J. H. Arabian // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 21-23.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1905
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	optimization	uk_UA
dc.subject	semiconductors	uk_UA
dc.subject	testing	uk_UA
dc.subject	process	uk_UA
dc.subject	mapping	uk_UA
dc.subject	modeling	uk_UA
dc.title	Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication