Публікація:
Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

dc.contributor.authorArabian, J. H.
dc.date.accessioned2016-09-01T10:35:22Z
dc.date.available2016-09-01T10:35:22Z
dc.date.issued2009
dc.description.abstractTESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.uk_UA
dc.identifier.citationArabian, J. H. Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation / J. H. Arabian // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 21-23.uk_UA
dc.identifier.urihttp://openarchive.nure.ua/handle/document/1905
dc.language.isoenuk_UA
dc.publisherХНУРЭuk_UA
dc.subjectoptimizationuk_UA
dc.subjectsemiconductorsuk_UA
dc.subjecttestinguk_UA
dc.subjectprocessuk_UA
dc.subjectmappinguk_UA
dc.subjectmodelinguk_UA
dc.titleOptimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulationuk_UA
dc.typeArticleuk_UA
dspace.entity.typePublication

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