Metastability Testing at FPGA Circuit Design using Propagation Time Characterization

Публікація:
Metastability Testing at FPGA Circuit Design using Propagation Time Characterization

dc.contributor.author	Rogina, B. M.
dc.contributor.author	Škoda, P.
dc.contributor.author	Skala, K.
dc.contributor.author	Michieli, I.
dc.date.accessioned	2016-09-02T10:57:46Z
dc.date.available	2016-09-02T10:57:46Z
dc.date.issued	2010
dc.description.abstract	This paper describes the measurement method and experimental technique with advanced instrumentation setup for analysing the metastability behavior and performance measurement of flip-flops used in programmable logic devices. In order to demonstrate this testing approach, the results for metastable characteristics parameters of one FPGA digital circuit fabricated commercially in 90 nm CMOS process are presented. The same test methods can also be used for evaluation of timing reliability in digital circuits as well.	uk_UA
dc.identifier.citation	Metastability Testing at FPGA Circuit Design using Propagation Time Characterization / B. M. Rogina and all // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 4-8.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2002
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	propagation time	uk_UA
dc.subject	testing	uk_UA
dc.subject	metastability	uk_UA
dc.subject	terms—FPGA	uk_UA
dc.title	Metastability Testing at FPGA Circuit Design using Propagation Time Characterization	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication