A VHDL Implemetation of the Advanced Encryption Standard

Публікація:
A VHDL Implemetation of the Advanced Encryption Standard

dc.contributor.author	Loban, H.
dc.date.accessioned	2019-09-27T11:52:33Z
dc.date.available	2019-09-27T11:52:33Z
dc.date.issued	2019
dc.description.abstract	A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered.	uk_UA
dc.identifier.citation	Hanna Loban. A VHDL Implemetation of the Advanced Encryption Standard. // First International Scientific and Practical Conference «Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs» MC&FPGA-2019, Kharkiv, Ukraine, July 26-27, 2019. – Kharkiv: NURE, MC&FPGA, 2019. – P. 37-38. DOI: 10.35598/mcfpga.2019.014	uk_UA
dc.identifier.uri	https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-014
dc.identifier.uri	https://doi.org/10.35598/mcfpga.2019.014
dc.identifier.uri	http://openarchive.nure.ua/handle/document/9835
dc.language.iso	en	uk_UA
dc.publisher	NURE, MC&FPGA	uk_UA
dc.subject	AES	uk_UA
dc.subject	triple DES	uk_UA
dc.subject	encryption	uk_UA
dc.subject	decryption	uk_UA
dc.subject	FPGA	uk_UA
dc.subject	VHDL	uk_UA
dc.title	A VHDL Implemetation of the Advanced Encryption Standard	uk_UA
dc.type	Thesis	uk_UA
dspace.entity.type	Publication