Reduction of Hardware Amount for Control Unit with Address Transformer

Публікація:
Reduction of Hardware Amount for Control Unit with Address Transformer

dc.contributor.author	Barkalov, A. A.
dc.contributor.author	Titarenko, L. A.
dc.contributor.author	Lavrik, A. S.
dc.date.accessioned	2016-08-26T10:10:54Z
dc.date.available	2016-08-26T10:10:54Z
dc.date.issued	2009
dc.description.abstract	The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given.	uk_UA
dc.identifier.citation	Barkalov, A. A. Reduction of Hardware Amount for Control Unit with Address Transformer / A. A. Barkalov, L. A. Titarenko, A. S. Lavrik // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 29-33.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1883
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	CPLD	uk_UA
dc.subject	CMCU	uk_UA
dc.subject	address transformer	uk_UA
dc.title	Reduction of Hardware Amount for Control Unit with Address Transformer	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication

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