Optimal Memory Tests Coding for Programmable BIST Architecture

Ivaniuk, A. A.

Публікація:
Optimal Memory Tests Coding for Programmable BIST Architecture

dc.contributor.author	Ivaniuk, A. A.
dc.date.accessioned	2016-09-01T10:51:14Z
dc.date.available	2016-09-01T10:51:14Z
dc.date.issued	2008
dc.description.abstract	Programmable memory BIST architecture is becoming a necessity for embedded memory cores. Classical memory BIST architectures use fixed algorithmic tests during the whole live of digital device. To improve the flexibility of memory BIST the programmable solution, based on finite state machine with microcode control, was invented. The requirement to use such flexibility is dictated by reason to use newest test for memory cores. In this paper a new Programmable Memory BIST architecture with small microcode memory is proposed. The analysis of existing March tests allows to code them into the optimal binary format, which cause not only small hardware overhead but also may speed-up the transferring of new test over the serial interfaces like IEEE 1149.1 and P1500.	uk_UA
dc.identifier.citation	Ivaniuk, A. A. Optimal Memory Tests Coding for Programmable BIST Architecture / A. A. Ivaniuk // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 4. – С. 32-37.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1910
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	finite state machines	uk_UA
dc.subject	built-in testing	uk_UA
dc.subject	memory testing	uk_UA
dc.title	Optimal Memory Tests Coding for Programmable BIST Architecture	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication