Публікація:
Optimal Memory Tests Coding for Programmable BIST Architecture

dc.contributor.authorIvaniuk, A. A.
dc.date.accessioned2016-09-01T10:51:14Z
dc.date.available2016-09-01T10:51:14Z
dc.date.issued2008
dc.description.abstractProgrammable memory BIST architecture is becoming a necessity for embedded memory cores. Classical memory BIST architectures use fixed algorithmic tests during the whole live of digital device. To improve the flexibility of memory BIST the programmable solution, based on finite state machine with microcode control, was invented. The requirement to use such flexibility is dictated by reason to use newest test for memory cores. In this paper a new Programmable Memory BIST architecture with small microcode memory is proposed. The analysis of existing March tests allows to code them into the optimal binary format, which cause not only small hardware overhead but also may speed-up the transferring of new test over the serial interfaces like IEEE 1149.1 and P1500.uk_UA
dc.identifier.citationIvaniuk, A. A. Optimal Memory Tests Coding for Programmable BIST Architecture / A. A. Ivaniuk // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 4. – С. 32-37.uk_UA
dc.identifier.urihttp://openarchive.nure.ua/handle/document/1910
dc.language.isoenuk_UA
dc.publisherХНУРЭuk_UA
dc.subjectfinite state machinesuk_UA
dc.subjectbuilt-in testinguk_UA
dc.subjectmemory testinguk_UA
dc.titleOptimal Memory Tests Coding for Programmable BIST Architectureuk_UA
dc.typeArticleuk_UA
dspace.entity.typePublication

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