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Публікація Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints(EWDTW, 2006) Zaychenko, S.; Hahanov, V.; Zaharchenko, O.Today the Assertions Based Verification (ABV) is by all means the most effective verification technology for SoC designs. Assertions provide basic blocks for building functional verification concept. Assertions simply catch a lot of design errors on early phases. This paper suggests new effective algorithmic model for assertions checking within the testbench-based simulation. The algorithms for handling key temporal operators from Property Specification Language (PSL) are described. Paper demonstrates the advantages of the suggested model over existing equivalents - in simulation performance, verification efficiency and model extensibility. Obviously, the verification process is a very complex and a very expensive part of the modern SoC design cycle. This process consists of searching the model for mistakes, causing the design to violate the functional specification, localizing the problems reasons and applying the fixtures. According to the EDA industry experts opinion, the cost of verification in ASIC [1] designs often overheads the 70% of the entire project budget [2]. Such high cost of the system quality is driven by several factors, in particular: – A large amount of missed details and mistakes in the work of SoC designers in the RTL code, verification engineers mistakes in the testbenches, also, the inevitable ambiguities of the original design specification; – drawbacks in the choosen design flows, complicating the bugs localization and fixtures, missing the possibilities for early discovery of the typical problems; – relatively low performance and bugs within the selected automation tools, which reach the quality and performance goals much slower than the input design complexity raises. Resolving these problems altogether and degrading the SoC verification cycle cost is currently a primary goal for the entire EDA world [3]. Leading EDA companies and industry experts are focused on developing the new generation of complex design verification methods, which will be able to: – minimize the human participation in the routine design and verification procedures, which will obviously decrease the probability of mistakes in several times; – lead to catching the largest amount of problems on the early design phases, reducing the average fixture cost; – upgrade the performance and stability of the design verification systems by raising the abstraction level both for the SoC models and for the testing stimulus. There are two basic directions in modern SoC verification methods – dynamic methods [2,4], based on the simulation, and static, or formal methods [5,6], based on the mathematical proof of certain system properties without testing stimulus. There are also hybrid methods [7] used, which assume usage of the simulation and functional coverage results to improve the performance of formal methods. This work is focused on the assertions-based verification technology [8,9], playing its role both in dynamic and formal methods.Публікація Technology for Faulty Blocks Coverage by Spares(EWDTS, 2009) Hahanov, V. I.; Chumachenko, S. V.; Litvinova, E. I.; Zaharchenko, O.; Kulbakova, N.The technology for the minimum coverage of faulty blocks by spares when repairing the logic part of digital system-on-chip is proposed. The general provisions and rules of coverage for the matrix of configurable logic blocks (CLB) with faulty cells are considered. Coverage criteria for faulty cells are developed. Examples of the algorithm implementation are made. Billions of digital systems-on-chips, used in the world, containing up to 16 types of various components (processor, memory, logic, buses, dedicated computers), which can be divided into 2 subsets: the memory (90%) and logic (10%). At that faults, detected in memory, are repaired successfully by the onchip facilities of the leading companies (Virage Logic, Intel). But almost 10% of logic is unamenable to regular solutions in the on-chip repair. Today, the world's biggest problem in the market of electronic technology is repairing the logic part of digital system-on-chip. Due to high market appeal the problem of diagnosis and repair of memory and logic cells is considered in the paper. It is one of the Gartner's Top 10 Strategic Technologies for 2009 that is solved by readdressing faulty cells to faultless components from the spare rows, columns and tiles. The strategy works on the logic blocks, which must be addressed (and should be provided with repair blocks) or reprogrammable on the faultless space of the chip for the embedded repair. Repair models for SiP memory modules are considered in the papers [1-6]. It should also take into account that the level of sales of computers has fallen in the 2 quarter of 2009 by 8% and amounted to 66 million pieces, but sale of laptops has grown by 20%. With regard to market of chips, there is the highest rise of sales in the last 13 years. This fact confirms Moore's Law – transistor today is worthless, a user will pay for power. The whole world sees the future of digital systems-on-chips. Conclusion – all market-based ideas will be implemented in the chip with a dedicated functionality. So, Infrastructure IP creation in a chip is important problem, because it is capable to realize the embedded diagnosis and repairing, which will significantly improve the yield and extend the life cycle of digital product. Therefore, any new solution in this area might be interesting for the market of electronic technology, which determines the urgency of the proposed technology for quasi-optimal faulty blocks coverage by spare components. The papers [7-9] are devoted to the development of the theory and methods for optimization of geometric design, in particular, the research of optimization placement problem for rectangular objects. The optimization placement problem for rectangular objects with variable metric characterizations in a given area is considered in [7, 8]. The analysis of advanced technologies for embedded Functional Intellectual Property of digital system-in-package is shown in [10]. Features of the architecture «System-in-Package» and present repair strategies for digital systems-on-chips, as well as the method of evaluation the reliability of their performance are considered. The problem of SoC testing technologies adaptation to new digital system embodiment System-in-Package (SiP) that allows implementing on-chip sophisticated specialty computers and RF devices is considered in [10]. System-in-Package forms new objectives and goals of Infrastructure IP for real time SiP functionality, which differ from embedded SoC diagnosis essentially. Structure-logical diagnosis and repair methods for FPGA functional logic blocks based on real time fault detection table analysis are proposed. A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed in [10]. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The objective of the research is the development of technology for the optimal faulty blocks coverage by spares when repairing the logic of digital SoC. Research tasks are: 1) The development of generalities and rules to cover the matrix of configurable logic blocks with faulty cells. 2) The development of coverage criteria for faulty cells. 3) Flowcharting for the bypassing the matrix of configurable logic blocks to obtain coverage. 4) Flowchart examples.