Перегляд за автором "Yeliseev, V."

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  • Зображення мініатюри
    Публікація
    Hierarchical hybrid approach to complex digital systems testing
    (EWDTW, 2005) Hahanova, I. V.; Obrizan, V.; Ghribi, W.; Yeliseev, V.; Ktiaman, H.; Guz, O. A.
    This paper offers approach to complex digital system testing based on hierarchy scaling during diagnosis experiment. Several models of testing are proposed. Main principles of testing system organization are given. Such approach allows significant reducing overall system testing and verification time.
  • Зображення мініатюри
    Публікація
    Hierarchical Systems Testing based on Boundary Scan Technologies
    (EWDTW, 2006) Hahanov, V. I.; Melnik, D.; Yeliseev, V.; Hahanova, A. V.
    We propose models of complex program-technical systems testing; these models solve diagnosis tasks in real time. Models use IEEE standard boundary scan technologies to observe internal lines, and methods of testability evaluation to define critical places in digital objects. Models and methods are oriented to test distributed control systems of critical technologies. Basic requirements for modern informational and control systems for complex objects and critical technologies are: 1) provide high reliability during operation; 2) online monitoring and control of all the parameters of critical system of object; 3) testing, diagnostics and repair in technically and standard acceptable time; 4) provide desired diagnosis depth of system or its components, automatically and in real time. New generation of modern technologies and design flows introduces additional criteria, related to design, manufacture and operation of digital devices: time-tomarket, Design-for-Manufacturability, Testability, Diagnosis, Verification. Major design stage is verification process, aimed to eliminate all design errors on the early stages; it leads to considerable time and costs savings. Acceptable testable overhead (assertion), added at early design stage, is interesting here, because it considerable decreases main parameter – time-to-market, using verification and testing methods; it is very urgent and attractive design model. Talk is about use of verification test, obtained at system design stage, to check device with minimal additional hardware and software expenses using boundary scan technologies. At the same time, hardware/software overhead mechanism must include additional control points, which must be introduced into design using Boundary Scan Register of special (ad-hoc) technologies at synthesis stage. As a result, design redundancy created once maybe used many times to check components of digital system during all stages of its lifecycle. At present, complex digital devices are considered as objects with several levels of hierarchy. At the lowest level, system is represented as a set of modern integrated circuits (PLD, ASIC), which implements SoCs, NoCs, memory, processors. Second level is formed by system on boards, where integral circuits are represented as primitives. Third level represents set of boards, which integrated into crates. Fourth level combines set of crates or boxes into complex distributed control system of technological process, manufacturing or critical technologies (aviation, cosmonautics, nuclear-power engineering, meteorology, defense, ecology). Fifth level may be considered as geographically distributed system, e.g. Internet. In this research, we consider from first to fourth levels of hierarchy, in order to creation of models and methods of its testing with defined diagnosis depth. Research objective – considerable decrease of complex digital system testing time during operation based on creation of general model of organization and execution of diagnostic experiment, including unconditional algorithms of faults finding using IEEE standards of testable design. Research problems: 1) choosing appropriate methods and tools for testing of all mentioned levels of hierarchy; 2) development of hierarchical model of organization and execution of diagnostic experiment, including conditional and unconditional algorithms of faults finding, oriented to testable design standards; 3) practical implementation of complex digital devices testing models and experimental evaluation.