Перегляд за автором "Syrevitch, Ye."
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Публікація High level FSM design transformation using state splitting(EWDTW, 2005) Kulak, E.; Kovalyov, E.; Syrevitch, Ye.; Grankova, E.One of the problems in the testbench generation for extended finite state machines (EFSM) is existence of internal variables. In fact the usage of these variables in the condition of transition increases real quantity of states by orders. Even for a variable with bit length 20 it leads to the state explosion problem. But for some control unit it is possible to make redesign of the project by including state variables to state register. The transformation algorithm contains phases of state splitting, transition splitting, unreachable (dead) state reduction and equivalent states minimization. The results of such transformation can be used for design analysis, optimization, validation, verification, synthesis and implementation. This paper was motivated by author’s work in the project ASFTest – a testbench generator for Aldec finite state machines. Graphical user interface used in state-of-the-art software allows to create environment for design entry with finite state machine abstract usage. Such form of design description is used in many software and hardware design tools like StatedCAD, FPGA Advantage, Stateworks, Stateflows, etc. The algorithm is described in the graphical way using the extended FSM notation. VHDL is chosen as target language. Synthesis is made by Xilinx synthesis tool which is included in Xilinx Webpack environment. The target device is CPLD Coollrunner II.Публікація Path Sensitization at Functional Verification of HDL-Models(EWDTW, 2006) Shkil, A. S.; Syrevitch, Ye.; Karasyov, A.; Cheglikov, D.Strategy of verification of digital devices models, represented in hardware description languages, is considered. The basic idea is in using path sensitization method in a graph model, generating distinguishing tests for separate functional elements, superposing these tests and interactive calculating etalon reactions. The necessity of researches in the field of verification is caused by the lack of effective methods and tools of functional verification of digital devices (DD) models on a step of describing them on behavioral level. World companies – vendors of digital circuits, are forced to decrease their time-to-market. According to vendors’ evaluations, verification (functional as well) takes up to 80% of labor expenditures in the design cycle. There is a big demand for tools of functional verification of devices models on a step of their description in hardware description language (HDL) on behavioral level. If model description in hardware description languages (HDL) is considered as a software program, then, from one point of view it is necessary to execute software verification, but the other point of view it is not always optimal. Software verification considers all modes with all data testing. While checking correspondence between code, which describes a device, and its specification on all possible data for all reachable inputs, to hold on verification during appropriate time with 100% completeness it is not possible. Assume that all in-build operators are combinational elements. It means that to check them it is necessary to drive 2n values, where n – total dimension of inputs. To get high quality of verification for appropriate time it is necessary to decrease number of driven tests. Despite variety of publications, connected with verification and diagnostics of digital devices, today instrumental tools of automatic test generation for complex DD functional verification are actual and claimed. Lack of automatic test generators is felt in many well-known companies: Aldec, Altera, Actel, Xilinx, Synopsis. Thus, this work aim is to develop HDL-models verification strategy, which allows decreasing time on design cycle by decreasing number of test vectors.Публікація The Method of Fault Backtracing for HDL - Model Errors Searching(EWDTS, 2009) Kucherenko, D. E.; Karasyov, A.; Syrevitch, Ye.In this paper the method of design error searching in non-structured HDL-code was considered. The method of backtracing was developed. An experiment on HDLmodel of digital device using this method was carried out. In modern CAD tools the basic way of device description is usage of hardware description languages, i.e. VHDL or Verilog, which allow making SOC design process faster. World companies – vendors of digital circuits, are forced to decrease their time-tomarket. Verification of digital projects, that is hardware or built-in hardware-software systems described in a Hardware Description Language - HDL, is the important task during designing digital devices. Often more than 70% of development time is spent on search and correction of mistakes in the project. Process of diagnosing is based on: DD model, allowing carrying out tests generation; designing errors, characteristic for HDL-models; algorithm of tests generation; methods of design errors search. Within the framework of technical diagnostics methods, there are several algorithms of defects search: based on available tests and known function of the device (functional algorithms on the base of errors tables or functions of errors tables), and based on the structure of the device (structural algorithms on the base of a reachability matrix). The purpose of the given work is to develop methods of defects/errors search in a non-structured HDL-code, allowing to reduce time of carrying out of diagnostic experiment and to reduce length of the diagnosis. Proceeding from the aforesaid, it is necessary to solve a task of adaptation of the method of backtracing at verification of HDL-models and to carry out diagnostic experiments on defect/design error search within the framework of verification.Публікація Verification tests generation features for microprocessor- based structures(EWDTW, 2004) Krivoulya, G. F.; Shkil, A. S.; Syrevitch, Ye.; Antipenko, O.A model of a microprocessor - based device as a bichromatic multidigraph with vertexes of two types is offered. Test generation features for functional testing using the updated algorithm of path activation in a structural model are described. The range method of data representation of different format data is introduced. Algorithms for execution of direct implication and backtracing of different types of operations and their program realization are represented. All set of methods of the determined test generation for digital devices can be divided into two large groups: structural and functional. Originally structural methods were oriented to a gate level of model performance of digital devices. However growth of complexity and rise of a component integration have led to a fact that models of increased integration elements began to be applied as the primitive elements (PE) of devices [1,2]. To the advantages of such approach it is possible to refer simple construction of a model of the device and formalizing of test generation procedures, and to the lacks - large dimension of a device model; and difficulties on creation and maintaining of the library of PE models, which can contain hundreds components. With the purpose of overcoming these lacks the functional approach to construction of the tests was developed and has received a wide circulation [3, 4]. It can be used for digital devices of any complexity, including microsystems with program and microprogram control, as it allows receiving high level models of such devices. However functional methods are badly formalized because different types of function boxes, such as control block, operational block, address block etc. are present in microsystems. It is not obviously possible to formalize the method, which would have a possibility to handle so heterogeneous types of devices on the basis of the uniform approach. In the given work the method of tests generation which is further development of the functional approach is offered. On a design stage of the digital device its decomposition on so-called homogeneously tested segments is carried out. The authors consider a method of tests generation for one of types of segments, namely, for the operational device (OD).