Перегляд за автором "Shkil, O. S."
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Публікація Analysis of the state diagram correctness of automatic logic control systems on FPGA paper(2019) Shkil, O. S.; Rakhlis, D. Y.; Kulak, E. M.; Filippenko, I. V.; Miroshnyk, M. M.; Hoha, M. V.The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.Публікація Design of real-time system logic control on FPGA(2019) Myroshnyk, M.; Shkil, O. S.; Kulak, E.; Rakhlis, D.; Filippenko, I.; Hoha, M.; Malakhov, M.; Sergienko, V.Problems of real-time hardware logic control systems design on the FPGA are considered. The control algorithm is implemented based on a timed FSM model,represented by a temporal state diagram. The design of the control device model using hardware description language VHDL in the form of the three-process pattern is made. The functional verification of the model was carried out using Active-HDL tools, the synthesis of the circuit was carried out on the Spartan 3E FPGA technology platform using Xilinx ISE CAD tools. The hardware costs for the circuit implementation of the control device were analyzed.Публікація Synchronizing sequences for verification of finite state machines(2019) Shkil, O. S.; Rakhlis, D. Y.; Kulak, E. M.; Miroshnyk, M. V.; Pahomov, Y. V.; Miroshnyk, A. M.Abstract—The method of detection and localization of design errors in HDL-models of finite state machines with arbitrary output functions was proposed. The diagnostic experiment is carried out bypassing all arcs of the Mealy machine, starting from the initial vertex, including for machines of the "non- exclusive" class. To ensure the return of the machine with a possible design error in the initial state, it is suggested to use synchronizing sequences. Diagnostic experiments were performed in the Active-HDL design environment.Публікація Testable design of control digital automatic machines(2020) Shkil, O. S.; Rakhlis, D. Y.; Kulak, E. M.; Filippenko, I. V.; Miroshnyk, M. M.Abstract—The aim of the work is to analyze hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM’s states depending on the presence of an unconditional transition, a conditional transition, and the absence of transitions between states of analyzed FSM. The conclusion on additional hardware costs is made on the basis of a comparison of synthesis results of testable HDL-models by means of CAD FPGA. The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state. The best way to organize additional transitions during setting of control FSM in an arbitrary state is the transition for which the total hardware cost estimate for the excitation functions is minimal, taking into account the coding of FSM’s states.Публікація Verification of FPGA control systems by analyzing the correctness of state diagrams(2020) Shkil, O. S.; Rakhlis, D. Y.; Kulak, E. M.; Filippenko, I. V.; Miroshnyk, A. M.; Miroshnyk, M. M.The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.