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Публікація Algebra-Logical Repair Method for FPGA Logic Blocks(EWDTS, 2009) Hahanov, V.; Galagan, S.; Olchovoy, V.; Priymak, A.At present there are many scientific publications, which cover SoC/SiP testing, diagnosis and repair problems [1-16, 19-20]. The testing and repair problem for the digital system logic components has a special place, because repair of faulty logic blocks is technologically complicated problem. Existing solutions, which are proposed in published works, can be divided on the following groups: 1. Duplication of logic elements or chip regions to double hardware realization of functionality. When faulty element is detected switching to faultless component by means of a multiplexer is carried out [4]. The FPGA models, proposed by Xilinx, can be applied for repair of Altera FPGA components. At repair the main unit of measure is row or column. 2. Application of genetic algorithms for diagnosis and repair on the basis of off-line FPGA reconfiguration not using external control devices [5]. The fault diagnosis reliability is 99%, repair time is 36 msec instead of 660 sec, required for standard configuration of a project. 3. Time-critical FPGA repairing by means of replacement of local CLBs by redundant spares is proposed in [6,7]. In critically important applications the acceptable integration level for CLB replacement is about 1000 logic blocks. The repair technologies for digital system logic, implemented on-chip FPGA, are based on existence or introduction of LUT redundancy after place and route procedure execution. Physical faults, which appear in the process of fabrication or operation, become apparent as logical or temporary failure and result in malfunction of a digital system. Faults are tied not only to the gates or LUT components but also to a specified location on a chip. The idea of digital system repairing comes to the removal of a fault element by means of repeated place and route executing after diagnosis. At that two repair technologies are possible: 1) Blockage of a defective area by means of developing the control scripts for long time place and route procedure. But it is not always acceptable for real time digital systems. The approach is oriented to remove the defective areas of any multiplicity. Blockage of the defective areas by means of repeated place and route executing results in repair of a digital system. 2) Place and route executing for repairing of real time digital systems can result in disastrous effects. The technological approach is necessary that allows repairing of the digital system functionality for milliseconds, required for reprogramming FPGA by new bitstream to remove defective areas from chip functionality. The approach is based on preliminary generation of all possible bitstreams for blocking future defective areas by means of their logical relocation to the redundant nonfunctional chip area. The larger a spare area the less a number of bitstreams, which can be generated a priori. Concerning multiple faults, not covered by a spare area, it is necessary to segment a digital project by its decomposition on disjoin parts, which have their own Place and Route maps. In this case a digital system that has n spare segments for n distributed faults can be repaired. The total chip area consists of (n+m) equal parts. The research objective is to develop a repair method for FPGA logic blocks on the basis of using the redundant chip area. Problems: 1) Development of an algebra-logical repair method for logic blocks of a digital system on basis of FPGA. 2) Development of a method for logic blocks matrix traversal to cover FPGA faulty components by spare tiles. 3) Analysis of practical results and future research.Публікація Cyber Physical Social Systems – Future of Ukraine(EWDTS, 2014) Hahanov, V.; Gharibi, W.; Kudin, A. P.; Hahanov, I.; Ngene, C.; Yeve, T.; Krulevska, D.; Yerchenko, A.; Mishchenko, A.; Shcherbin, D.; Priymak, A.A fundamental solution of topical problem for economic, social and technological future of Ukraine and the world is proposed. The problem lies in the elimination of corruption through the formation and implementation of the state program «Creation of Cyber Physical Space for Digital Monitoring Technological Processes and Optimal Resource Management in order to Achieve Socially Important Goals». The cyber technology for human-free managing social resources (staff and finance) includes two cloud service: 1) the distribution of government contracts and finance between the structures, undertakings and entities, based on competition of their competence matrices for a given metric; 2) allocation of staff vacancies in scalable social groups based on competition of the competence matrices of applicants for a given metric. The competence metric is a measuring method of the distance between objects or processes based on the use of the parameter vector that defines the space or a competence matrix of a person or social group in real time. A competence matrix is a model of integrated activity and skills of a person or social group at a given metric and time interval. As an alternative solution of the problem it is considered a cyber physical system for managing human and financial resources (Cyber Social Systems - CSS), as a scalable cloud service, available to the social groups, government agencies, private companies and private individuals; it provides lifelong monitoring competencies of corresponding subjects in real time in order to carry out cyber staff management through appropriate career, moral and material incentives according to the results of their constructive activity. The cyber social system is focused on the total destruction of the corruption in the actions of managers at all levels by eliminating the subjectivity in the management of human and financial resources on the basis of the transfer of the official functions to independent cloud cyber service. The system consists of two interacting components: 1) accumulative monitoring of all kinds of human (social group) activity that generates a competence matrix in realtime; 2) the optimal management through career, moral and material incentives of individuals and social formations based on the analysis and rating of the corresponding competence matrices. A cyber system is based on the use of the following technologies: Big Data, Internet of Things, Smart Everything, parallel virtual processors and focused on serving individuals, government agencies and companies. For each subject two unique metrics of competencies are generated: 1) the gold standard of indexes for each category of professional activity; 2) the current competence matrix of the subjects filled in the process of their life, which are ranked by metrical comparison or evaluation of the results of work with standard or better values.Публікація Models for Quality Analysis of Computer Structures(EWDTS, 2012) Murad, Ali Abbas; Chumachenko, S. V.; Hahanova, A. V.; Gorobets, A. A.; Priymak, A.The methods for estimating computational structures and searching the shortest paths between the pair of nodes are presented. A criterion for evaluating the effectiveness of computational structures based on the graph model of the functional blocks of digital systems-on-chips is developed. A modified Dijkstra's algorithm to determine the average cost of interconnections in computing architecture for every pair of nodes is proposed. Verification of the criterion, when evaluating the effectiveness of different topologies of computational structures is performed. Creating effective computational structures is related not only to increasing the speed of primitives, but also with the topology of interconnections between them, which can significantly improve the performance of parallel processing data due to additional expensive connections. It is therefore necessary to have criteria for evaluating performance, taking into account not only transaction time between the nodes, but the hardware redundancy, which considerably reduces the average time of receiving and transmission of information between the primitive computing components. Such criteria can be used to evaluate the effectiveness of graph models of local and global computer networks, urban infrastructure of road communications, as well as the traffic flows in order to identify bottlenecks affecting the traffic. The problem of finding such criteria is related to the minimization of the computational cost for determination of all possible minimal paths between nodes of pairs. The aim of research is development of criteria for evaluating the effectiveness of computational structures, based on graph model of interconnections of functional blocks, which make it possible to determine the quality of the topological architectures of digital systems-on-chips. The objectives: 1) Analysis of methods for estimating the computational structures and finding the shortest paths between nodes of pair. 2) Development of criteria for evaluating the effectiveness of computational structures, based on graph model of the functional blocks of digital systems-on-chips. 3) Modification of Dijkstra's algorithm to determine the average cost of interconnections of computing architecture for a node pair. 4) Verification of the criteria when evaluating the effectiveness of different topologies of computational structures.Публікація Quantum Models for Description of Digital Systems(EWDTS, 2013) Hahanov, V. I.; Hahanova, I. V.; Litvinova, E. I.; Priymak, A.; Fomina, E.; Maksimov, M.; Tiecoura Yves; Malek, Jehad Mohammad JararwehQuantum models for description of digital systems and results of studies concerning the models and methods of quantum diagnosis of digital systems, qubit fault simulation and analysis of fault-free behavior are presented. Quantum calculators are effectively used for faulttolerant design and solving optimization problems by way of the brute-force method through the use of set theory. A set of elements in the traditional computer is orderly, because each bit, byte or other component has its own address. Therefore, the settheoretical operations are reduced to exhaustive search of addresses of primitive elements. Address order of data structures useful for applications where model components can be strictly ranked, which makes it possible to carry out their analysis in a single pass (a single iteration). If there is not order in the structure, for example, the set of all subsets, the classical model of memory and computational processes disimprove the analysis time of primitive association equal by the rank, or processing of associative groups is ineffective. What can be offered for unordered data instead of the strict order? Processor, where the unit cell is the image or pattern of the universe of n primitives, which generates nQ 2 = all possible states of a cell as a power set or the set of all subsets. Direct solution about creating such cell is based on unitary positional coding states of primitives that form the set of all subsets and in the limit the universe of primitives by superposition of last ones. History of the issue of the necessity for developing quantum computing on the background of the technological revolution in nano-electronics fit in a few of clear theses: 1) Quantum Computer was created the experts in the field of quantum mechanics and electronics, who introduced the idea of creating a non-numeric analogbased computer. 2) The introduced notion of a qubit corresponds to the power set of primitives, which is the ideal nonnumeric form of object component description for analysis, synthesis and optimization of discrete objects. 3) The forms of qubit representation are the following: 1. The universe of primitive symbols, which generate the set of all subsets (power set). 2. Binary vectors, where the power set is a combination of unit values of primitives. 3. Hasse diagram, which forms the power set of all possible solutions on the graph. 4. Full transition graph, which determines the set of all subsets of transitions in the form of arcs. 5. The geometric representation in a plane for a qubit in the form of points and segments corresponding to the Boolean (power set). 4) In practice, more than 90% of all IT-industry problems associated with information retrieval in cyberspace, pattern recognition and decision-making are related to the field of discrete mathematics, where it is difficult to find a place of numerical arithmetic. 5) It is necessary to create associative logic brainlike parallel (quantum) processors, which effectively use Boolean (qubit) primitives or elements (sets) to solve problems of discrete mathematics. 6) Set-theoretic operations have to be replaced the isomorphic logical instructions (and, or, not, xor) for the subsequent creating a new system of parallel qubit programming to solve logic and optimization problems, based on qubit data structures. 7) Another solution for organization computing is associated with topological representation of the qubit, where the elements are the geometric shapes. 8) Nonnumeric problems, focused to the use of quantum processor are the following: minimization of forms of Boolean functions, when describing complex systems; searching paths in the graph; testing and diagnosis of digital systems; combinatorial studies of processes and phenomena; intelligent data searching, pattern recognition and decision making; discretization of fuzzy models and methods, when creating the intelligence; digital data processing and the developing efficient codec for DSP-devices.Публікація Spam Diagnosis Infrastructure for Individual Cyberspace(EWDTS, 2011) Hahanov, V. I.; Mischenko, A.; Chumachenko, S. V.; Hahanova, A. V.; Priymak, A.The theory, methods and the architecture of parallel information's analysis is presented by the form of analytical, graph and table forms of associative relations for the search, recognition, diagnosis of destructive components and the decision making in ndimensional vector cybernetic individual space. Vector -logical processes-models of actual oriented tasks are considered. They include the diagnostic of spam and the recovery of serviceability, the hardwaresoftware components of computer systems and the decision quality is estimated by the interactions of nonarithmetic metrics of Boolean vectors. The concept of self-development information of computer ecosystem is offered. It repeats the evolution of the functionality of the person. Original processes-models of associativelogical information analysis are represented on the basis of high-speed multiprocessor in n-dimensional vector discrete space. The problem of creating an effective infrastructure of cyberspace (Cyber Space), as well as selfdeveloping information and computing ecosystems (ICES) of the planet is particularly important for global companies, such as Kaspersky Laboratory, Google and Microsoft. Cyberspace as an object of nature is also susceptible to destructive components affecting the performance of subjects, which are computers, systems and networks. Therefore, now and in the future it remains as an important problem of space standardization and specialization of all the interacting entities, including the negative, as an integral part of the ecosystem. This action is permanent in time, whose purpose is to keep up, but one step ahead of the emergence of new malicious components, by creating an infrastructure cybernetic space, operating the computer ecosystem of the planet and the quality of each person's life.Публікація Verification and Diagnosis of SoC HDL-code(EWDTS, 2011) Hahanov, V. I.; Park, Dong Won; Guz, O. A.; Galagan, S.; Priymak, A.Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertionbased models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered. Recent trends in creating new communications, computing and information services, useful to the human, are development of dedicated gadgets, which have important advantages over PCs and laptops: power consumption, compactness, weight, cost, functionality, and friendliness of interface. Practically the top ten dedicated products 2010 (Apple iPad, Samsung Galaxy S, Apple MacBook Air, Logitech Revue, Google Nexus One (HTC Desire), Apple iPhone 4, Apple TV, Toshiba Libretto W100, Microsoft Kinect, Nook Color) is realized as digital systems-on-chips. By 2012 the mobile and wireless communication market will move to 20 nm (results of the January 2011 Technology Forum of Common Platform Alliance). Further development of the technologies by year: 2014 – 14 nm, 2016 – 11 nm. In 2015 more than 55% of mobile phones will be smartphones, tablet PCs will replace laptops and netbooks. Superfones (Nexus-1, Google) will unite all devices and services. The transition from the computing platform to mobile devices with small size results in considerable reduction in power consumption worldwide. The next computerization wave, entitled "Internet of things", is being accelerated. It will lead to widespread sensor networks, including their integration into the human body. The world market of the above devices and gadgets today involves about 3 billion products. For their effective designing, manufacturing and exploitation the new technologies and Infrastructures IP are created.