Перегляд за автором "Nikitin, D."

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  • Зображення мініатюри
    Публікація
    Practical results of the study of photopolymer exposure of printed circuit board topology
    (ISMA, 2023) Nevlyudov, I.; Razumov-Frizyuk, E.; Nikitin, D.; Badaniuk, I.; Strelets, R.
    Practical results of studies of deviations of geometric dimensions of the topological structure of printed circuit boards during photopolymer 3D exposure are presented. A series of experiments of topology exposure under different process parameters was carried out. The results of 112 samples were checked using statistical analysis and a regression model of the influence of parameters on the deviation of the geometric dimensions of conductors was built.
  • Зображення мініатюри
    Публікація
    Technology for creating the topology of printed circuit boards using polymer 3d masks
    (ХНУРЕ, 2021) Nevliudov, I.; Razumov-Fryzyuk, E.; Nikitin, D.; Bliznyuk, D.; Strelets, R.
    The subject of research is the influence of factors of exposure of two-dimensional images on the topology of conductors in the manufacture of printed circuit boards by the method of three-dimensional polymer photomasks. The purpose of the work is ensuring the accuracy and preservation of the geometric dimensions of the conductors of printed circuit boards during LCD exposure of masks on the work piece. To achieve this goal, it is necessary to solve the following tasks: to analyze photolithography technology and types of polymer 3D printing; to develop a technological process for exposing photopolymer masks to a printed circuit board blank using 3D printing technologies; to conduct experimental studies to determine the optimal exposure parameters; on the basis of the empirical results obtained, to calculate the correlation coefficients of the factors for recall; to construct a linear regression model of the dependence of the deviations of the geometric dimensions of the printed conductors on the parameters of solutions for etching and exposure conditions. Results: The constructed regression models will become the basis for creating a software database that optimizes the initial images of the topology of printed conductors in the automated production of printed circuit boards. This will simplify the process of developing the topology of printed circuit boards, taking into account the real influence of the parameters of the technological operations of etching and exposure on the thickness of the tracks of the conductors of the printed circuit boards, which will reduce the proportion of rejects in the manufacture of single- and double-sided printed circuit boards. Conclusions: an LCD exposure technology and a method for studying the effects of exposure factors on the quality of printed circuit board topology are proposed, which provide sufficient empirical data to create regression models for calculating the influence of technological factors on the final dimensions of conductive paths in the production of printed circuit boards. Further development of the proposed technology will make it possible to manufacture rigid and flexible printed circuit boards completely, with conductive paths, a dielectric base, electronic elements that can be used in various devices.
  • Зображення мініатюри
    Публікація
    Topological image processing for comprehensive defect and deviation analysis using adaptive binarisation
    (ХНУРЕ, 2023) Badanyuk, I.; Nevliudov, I.; Nikitin, D.
    The subject of this article is the preparation for recognition and comparison of real topological images of printed circuit boards (PCBs) using adaptive image binarisation with an "automatic window" (the area for scanning the image "Block size"). The aim of the work is to improve the method of adaptive binarisation for images obtained by technical vision systems by developing an automatic algorithm for detecting the required value of the image binarisation window. Objectives: to analyse the subject area for the analysis of technical images of the topology of the SOE; to describe the finding of the global binarisation threshold (t) using the "Otsu" method; to perform global image binarisation; to calculate the standard deviation of binarisation; to process the results obtained to find the required value of the Block size; to test the developed algorithm in software. Results: an image processing algorithm with automatic adjustment of the "Block size" binarisation window was implemented and tested; software was developed using the proposed algorithm and the performance of global binarisation with an improved method of finding the "Block size" values for scanning an image in processing small elements of the SE topology was compared. This will allow solving the following issues: noise removal – removing noise from the image (noise can occur due to poor scan or photo quality, as well as due to the presence of small spots on the surface of the PCB); image segmentation – dividing the image into separate elements such as contours, zones and text (this process can be automated using image processing software); element detection – finding and separating individual elements such as resistors, capacitors and other components depicted on the topology. Conclusions: according to the results of the work, an algorithm for automatically adjusting the size of the scanning area "Block size" for binarisation of technological images of the SE topology has been developed. The following advantages of this algorithm can be distinguished: automatic finding of the optimal scanning area Block Size; resistance to image noise without the use of smoothing filters; finding details in areas of contrast difference.