ElAr :: Перегляд за автором "Ngene, C. U."

Перегляд за автором "Ngene, C. U."

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Closer Look at Microprocessors that have Shaped the Digital World
(ХНУРЭ, 2009) Ngene, C. U.; Mishra, M. K.
If you have been following the development in the microprocessor world you would attest to the fact that things have dramatically changed since the introduction of the first world acclaimed microprocessor Intel 4004 in 1971. What were the changes that have been made to these processors that have actually improved our lots, especially how we perceive the world around us and improve our productivity at work? In this study, we investigate different general purpose processors with a view to enlightening consumers and enthusiasts alike, determine which of the myriads of processors will be most appropriate for their tasks and the choice of which makes more economic sense. We have been able to explore in relative detail that processor speed is not the only determinant of processor performance but of most significant is the architecture. This study reveals that new technology is not the only factor that determines whether a new processor is actually new, but most importantly marketing considerations have been the driving force.
Cloud Traffic Control System
(EWDTS, 2013) Ziarmand, A.; Hahanov, V. I.; Guz, O. A.; Ngene, C. U.; Arefjev, A.
A cloud service “Green Wave” (the intellectual road infrastructure) is proposed to monitor and control traffic in real-time through the use of traffic controllers, RFID cars, in order to improve the quality and safety of vehicle movement, as well as for minimization the time and costs when vehicles are moved at the specified routes. The evolution of cyber world is divided into the following periods: 1) the 1980s - formation of personal computers; 2) the 1990s - the introduction of Internet technologies in production processes and people's lives; 3) the 2000s - improving the quality of life through the introduction of mobile devices and cloud services, and 4) the 2010s - the creation of a digital infrastructure for monitoring and control of moving objects (air, sea, ground transportation, and robots). Therefore, in the present market feasible problem is the system integration of monitoring-control cloud service and transport RFID blocks as well as digital tools of road infrastructure for optimal on-line vehicle and traffic control in order to address the social, human, economic and environmental problems. What is the basic of the world cyberspace? – The silicon chip and its analogs. Modern microelectronics enables to create not flat but three-dimensional transistor structures (3D – FinFETs) in 14 nm range, commensurate with the size of the atom. This means the appearance in the near future 3D-System-on-Chip instead of flat structures or system-in-package. The advantages of the chips significantly affect the characteristics of industrial products in terms of: energy consumption, dimensions, performance, cost and quality due to reducing not only the dimension of the components, but also the relationships between them. Thus there arise problems associated with heat removal from the internal area of 3D-chip, as well as the creation of new technologies for designing, verification, testing, diagnosis and repairing of its components. Thus, a microworld of cyberspace goes in 3Dmeasurement not easily. Macroworld remains flat when components, computers, networks, cloud services of cyberspace are combined into the system. Which arguments could be made for the transfer of the macroworld in 3D-space? They are the following: the compactness of information, the performance of searching in cyberspace, and its dimension. The triangular flat structure of the system where all nodes are adjacent has a major drawback in the two dimensions – for encoding three nodes or edges it is necessary three codes, and this means that one code of two-bit vector is not used. Therefore, the creation of a primitive structure, where all nodes are adjacent and their number is four to make full use of the two bits code space, means re-open an amazing 3D-figure - a tetrahedron! It has six edges or distances, xor-sum of which is equal to zero. When descripting the figure two edges are redundant, which can be used to reduce the volume of information up to 66% during storage and transfer of data. Formation of cyberspace through the use of primitive tetrahedra allows optimizing (minimizing) the ratio of the structural complexity of the space to the average distance between two points. Object of research is technologies for monitoring and management of vehicles integrated with cloud services, based on the use of the existing road infrastructure, RFID, radar and radio navigation. Subject of research: traffic and road infrastructure of Ukraine and its regions, as well as advanced software and hardware RFID systems for monitoring and road management, based on the use of road controllers, global systems for positioning, navigation (GPS, GPRS), and cloud services in the Internet. The essence of research is creation of intellectual road infrastructure (IRI) – cloud service "Green Wave" for monitoring infrastructure and management of road in real-time, based on creating virtual road infrastructure (Fig. 2), integrated with road traffic controllers, RFID of vehicles in order to improve the quality and safety of vehicle movement, minimization of time and costs when realization of routes.
Synthesis of Qubit Models for Logic Circuits
(EWDTS, 2012) Zaychenko, S. A.; Gharibi, W.; Dahiri Farid; Hahanova, Yu. V.; Guz, O. A.; Ngene, C. U.; Adiele Stanley
Qubit (quantum) structures of data and computational processes for significantly improving performance when solving problems of discrete optimization and fault-tolerant design are proposed. We describe superpositional method for synthesizing cube of functionality for its implementation in the structural components of programmable logic chips. The estimates of synthesis time, as well as hardware costs for creating qubit models of logic circuits are represented. Quantum computing becomes interesting for cyberspace analysis, creating new Internet technologies and services, which is explained by their alternative to the existing models of computing processes. Market appeal of quantum (qubit) models is based on the high parallelism when solving almost all discrete optimization problems, factoring, minimization of Boolean functions, effective compression of data, their compact representation and teleportation, fault-tolerant design through significant increase in hardware cost. But now it is acceptable, because there are problems of use silicon chip, which contains up to 1 billion gates on a substrate thickness 5 microns. At that modern technologies allow creating a package (sandwich) containing up to 7 chips, which is comparable with the quantity of the human brain neurons. Practically, through-silicon via (TSV) connection is based on the technological capability of drilling about 10 thousand through vias in 1 square centimeter of wafer or die. Layout the indicated volume of useful functionality on chip is currently problematic. So, it is necessary to develop hardwarefocused models and methods for creating high-speed tools of parallel solving real world problems. Considering the discreteness and multiple-valuedness of the alphabets for description of information processes, the parallelism, inherent in the quantum computing, is particularly actual when developing effective and intelligent engines for cyberspace or Internet, tools for synthesis of fault-tolerant digital primitives and systems, testing and simulation of digital systems-on-chips, technologies for information and computer security, brain-like models for computing, analysis and synthesis of linguistic constructions.
Testing and Verification of HDL-models for SoC components
(EWDTS, 2009) Hahanova, I. V.; Hahanov, V.; Ngene, C. U.; Yves, T.
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-tomarket) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed. The novel testing and verification technology for system HDL models allows searching for errors in the HDL-code with a given thoroughness for an acceptable time by means of the introduction assertion redundancy to the critical points of the software model, which are defined by the synthesized logic functions of the testability. The controllability and observability criteria, used in hardware design and test, are applied to estimate the quality of software code in order to improve it and effective diagnose semantic errors. The objective is improvement of the testing and verification technology for digital systems to diagnose and correct of errors for HDL-models by sharing of the assertion engine and testable design technologies. The research tasks: 1. Design verification and testing environment for system HDL-model on the basis of assertions. 2. Development of testability evaluation metrics on the basis of new logic testability function. 3. Application of a technological assertion model to verify an IP-core filter on the basis of discrete cosine transform. 4. Practical results and directions for further research. The research sources: 1. Technologies and tools of test and testbench creation are represented in the papers [1-3]. 2. Models and methods for verification of the system models on the basis of assertions are described in [4-7]. Testable software design uses the IEEE standards [8-10], as well as innovative solutions to verify and testability analysis for the system HDLmodels [11-18].
The Essentials of Testing Digital Circuits
(ХНУРЭ, 2012) Ngene, C. U.
Testing is an important part of digital devices development life cycle and it takes about 70% of time to market. This paper discusses the various testing concepts as it relates to digital design and how it impacts the reliability of the final product. We also show that making designs testable by using appropriate design for testability techniques considerably reduces testing time and ensures a fine-grained diagnosis of finished product. A three bit counter circuit was used to illustrate the benefits of design for testability by using scan chain methodology.
Модели генерации тестов и методы диагностирования SOC-компонентов
(ХНУРЭ, 2011) Yves, T.; Ngene, C. U.; Литвинова, Е. И.; Хаханов, В. И.; Александров, В. И.
Предлагается структурная модель отношений компонентов (функциональность, устройство, тест, дефекты), которая позволяет определять и классифицировать пути решения практических задач, включая синтез тестов, моделирование неисправностей и поиск дефектов. Описываются методы синтеза тестов для функциональностей, заданных матричными формами описания поведения цифровых компонентов, которые отличаются параллелизмом векторных операций над таблицами. Предлагаются усовершенствованные методы поиска функциональных нарушений, которые дают возможность существенно повысить быстродействие вычислительных процедур, связанных с диагностированием и восстановлением работоспособности программных и аппаратных продуктов. Модели и методы синтеза тестов для функциональностей и диагностирования нарушений могут быть использованы в качестве встроенных компонентов инфраструктуры сервисного обслуживания цифровых систем на кристаллах с применением стандарта граничного сканирования IEEE 1500.
Мультипроцесорна архітектура паралельного рішення асоціативно-логічних завдань
(Науково-технічний журнал : Інформаційно - керуючі системи на залізничному транспорті, 2010) Хаханов, В. І.; Литвинова, Є. І.; Гузь, О. А.; Ngene, C. U.
Запропоновано архітектуру швидкодіючого мультипроцесора паралельного аналізу інформації, представленої у вигляді аналітичних, графових і табличних структур асоціативних відношень, для пошуку, розпізнавання та прийняття рішень у n-вимірному векторному дискретному просторі. Розглядаються векторно-логічні процес-моделі актуальних прикладних задач, якість рішення яких оцінюється введеною інтегральною неарифметичною метрикою взаємодії булевих векторів.
Сервісне обслуговування сучасних цифрових систем на кристалах
(Науково-технічний журнал : Радіоелектронні і комп'ютерні системи (РЕКС), 2009) Хаханов, В. І.; Литвинова, Є. І.; Ngene, C. U.
Рассматривается проблема адаптации технологий тестирования цифровых систем на кристаллах (System on Chip – SoC) для нового конструктивного поколения цифровых систем – System-in-Package (SiP), позволяющего эффективно и компактно имплементировать в кристаллы сверхсложные специализированные вычислительные и радиочастотные устройства для рынка электронных технологий. Вместе с тем пакет кристаллов формирует спектр новых задач сервисного обслуживания SiP-функциональностей в реальном масштабе времени, которое существенно отличается от процессов встроенного диагностирования SoC. В связи с этим предлагается алгебрологический метод диагностирования и восстановления работоспособности функциональных логических блоков FPGA, основанный на использовании таблиц неисправностей и их анализе в реальном масштабе времени.
Тестирование и верификация HDL-моделей компонентов SOC. I
(ХНУРЭ, 2009) Хаханов, В. И.; Литвинова, Е. И.; Чумаченко, С. В.; Побеженко, И. А.; Ngene, C. U.
Предлагается технология тестирования и верификации системных HDL-моделей, ориентированная на существенное повышение качества проектируемых компонентов цифровых систем на кристаллах (yield) и уменьшение времени разработки (time-to-market) путем использования среды моделирования, тестопригодного анализа логической структуры HDL-программы для квазиоптимального размещения механизма ассерций.
Тестирование и верификация HDL-моделей компонентов SOC. II
(ХНУРЭ, 2009) Хаханов, В. И.; Литвинова, Е. И.; Побеженко, И. А.; Yves, T.; Ngene, C. U.
Предлагается алгебрологическая модель для вычисления критериев тестопригодности системных HDL-моделей, ориентированная на существенное повышение качества проектируемых компонентов цифровых систем на кристаллах (yield) и уменьшение времени разработки (time-to-market).
Технология тестирования и верификации системных HDL-моделей
(Науково-технічний журнал : Радіоелектронні і комп'ютерні системи (РЕКС), 2010) Хаханов, В. И.; Гузь, О. А.; Побеженко, И. А.; Ngene, C. U.
Технология позволяет осуществлять поиск ошибок с заданной глубиной в программном HDL-коде за приемлемое для разработчика время путем введения ассерционной избыточности в критические точки программной модели, определяемые с помощью синтезированных логических функций тестопригодности. Рассмотрены инновационные технологии тестопригодного проектирования программных и аппаратных продуктов, ориентированные на эффективную разработку тестов и верификацию компонентов цифровых систем на кристаллах. Таким образом, используемые в hardware design and test критерии управляемости и наблюдаемости применены для оценки качества программного кода в целях его улучшения и эффективного диагностирования семантических ошибок.

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