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Публікація Early Detection of Potentially Non-synchronized CDC Paths Using Structural Snalysis Technique(EWDTS, 2009) Zaychenko, S.; Melnik, D.; Lukashenko, O.The number of independent clock domains found on the typical today's device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >15-20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today's SoC design methodology; only static techniques can work as soon as the RTL starts taking shape. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis. The sections of logic elements that driven by clocks coming from different sources are called clock domains. The signals that interface between asynchronous clock domains are called the clock domain crossing (CDC) signals. The DATA_A signal is considered as an asynchronous signal into the receiving clock domain (no constant phase and time relationship exists between CLK_A and CLK_B).The nature of CDC bugs is intermittent; it simply means that a test suite can be successfully completed on a chip in the morning, but the same tests will complete with errors for the same chip in the afternoon. Consider the simplest flip-flop example: such a flip-flop is located anywhere in the chip; the data signal for this flip-flop comes from the domain #A but the clock signal — from the domain #B... so whenever the setup or hold condition is violated, the flip-flop can go to one or to zero and it cannot be predicted.Публікація Hierarchical Systems Testing based on Boundary Scan Technologies(EWDTW, 2006) Hahanov, V. I.; Melnik, D.; Yeliseev, V.; Hahanova, A. V.We propose models of complex program-technical systems testing; these models solve diagnosis tasks in real time. Models use IEEE standard boundary scan technologies to observe internal lines, and methods of testability evaluation to define critical places in digital objects. Models and methods are oriented to test distributed control systems of critical technologies. Basic requirements for modern informational and control systems for complex objects and critical technologies are: 1) provide high reliability during operation; 2) online monitoring and control of all the parameters of critical system of object; 3) testing, diagnostics and repair in technically and standard acceptable time; 4) provide desired diagnosis depth of system or its components, automatically and in real time. New generation of modern technologies and design flows introduces additional criteria, related to design, manufacture and operation of digital devices: time-tomarket, Design-for-Manufacturability, Testability, Diagnosis, Verification. Major design stage is verification process, aimed to eliminate all design errors on the early stages; it leads to considerable time and costs savings. Acceptable testable overhead (assertion), added at early design stage, is interesting here, because it considerable decreases main parameter – time-to-market, using verification and testing methods; it is very urgent and attractive design model. Talk is about use of verification test, obtained at system design stage, to check device with minimal additional hardware and software expenses using boundary scan technologies. At the same time, hardware/software overhead mechanism must include additional control points, which must be introduced into design using Boundary Scan Register of special (ad-hoc) technologies at synthesis stage. As a result, design redundancy created once maybe used many times to check components of digital system during all stages of its lifecycle. At present, complex digital devices are considered as objects with several levels of hierarchy. At the lowest level, system is represented as a set of modern integrated circuits (PLD, ASIC), which implements SoCs, NoCs, memory, processors. Second level is formed by system on boards, where integral circuits are represented as primitives. Third level represents set of boards, which integrated into crates. Fourth level combines set of crates or boxes into complex distributed control system of technological process, manufacturing or critical technologies (aviation, cosmonautics, nuclear-power engineering, meteorology, defense, ecology). Fifth level may be considered as geographically distributed system, e.g. Internet. In this research, we consider from first to fourth levels of hierarchy, in order to creation of models and methods of its testing with defined diagnosis depth. Research objective – considerable decrease of complex digital system testing time during operation based on creation of general model of organization and execution of diagnostic experiment, including unconditional algorithms of faults finding using IEEE standards of testable design. Research problems: 1) choosing appropriate methods and tools for testing of all mentioned levels of hierarchy; 2) development of hierarchical model of organization and execution of diagnostic experiment, including conditional and unconditional algorithms of faults finding, oriented to testable design standards; 3) practical implementation of complex digital devices testing models and experimental evaluation.Публікація Structural Analysis Technique and Bad Synchronization Styles(ХНУРЭ, 2009) Melnik, D.; Lukashenko, O.This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis.Публікація Verification Challenges of Clock Domain Crossings(EWDTS, 2008) Zaychenko, S.; Melnik, D.; Lukashenko, O.This paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs.