Перегляд за автором "Kulak, E."

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  • Зображення мініатюри
    Публікація
    Design of real-time system logic control on FPGA
    (2019) Myroshnyk, M.; Shkil, O. S.; Kulak, E.; Rakhlis, D.; Filippenko, I.; Hoha, M.; Malakhov, M.; Sergienko, V.
    Problems of real-time hardware logic control systems design on the FPGA are considered. The control algorithm is implemented based on a timed FSM model,represented by a temporal state diagram. The design of the control device model using hardware description language VHDL in the form of the three-process pattern is made. The functional verification of the model was carried out using Active-HDL tools, the synthesis of the circuit was carried out on the Spartan 3E FPGA technology platform using Xilinx ISE CAD tools. The hardware costs for the circuit implementation of the control device were analyzed.
  • Зображення мініатюри
    Публікація
    Hierarchical Analysis of Testability for SoCs
    (EWDTW, 2006) Kaminska, M.; Hahanov, V. I.; Kulak, E.; Guz, O. A.
    This paper presents the strategy of testable SoC design procedure. This approach based on the testability analysis on different levels of abstractions (gate level, register transfer level, system level). Analysis is based on structural analysis of SoC. Proposed methods give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The main goal of the presented algorithms is to increase fault coverage before test generation and to decrease verification time. It could be reached by improving of testability and simplification of the verification task. As a complexity of today’s ASIC designs continues to increase, the challenge of verifying these designs intensifies at an even greater rate [1]. Testability is one of the most important factors that are considered at digital devices design along with reliability, speed and the cost. The low level of device testability leads to increasing of number of non-tested faults and verification time at design, production and operations stages. Therefore, the cost of diagnostic (a degree of faults concentration) decreases essentially during techniques of testability design. The cost of a fault essentially increases in the process of ASIC crystal implementation (Fig. 1). Hence analysis of testability needs to be done at earlier level of device description. This is the main reason of development of the methods of testability analysis at the different levels of abstraction: system, RT, and gate levels. Object under test – system on chip, which can be presented on different levels of abstraction. Goal of work – maximal decreasing of test procedure cost; to provide digital circuit testability on all design levels of abstraction, till device manufacturing stage. To provide device testing possibility with minimal test by adding of scan cells on bottlenecks in circuit (circuit’s parts, which hard to test).
  • Зображення мініатюри
    Публікація
    High level FSM design transformation using state splitting
    (EWDTW, 2005) Kulak, E.; Kovalyov, E.; Syrevitch, Ye.; Grankova, E.
    One of the problems in the testbench generation for extended finite state machines (EFSM) is existence of internal variables. In fact the usage of these variables in the condition of transition increases real quantity of states by orders. Even for a variable with bit length 20 it leads to the state explosion problem. But for some control unit it is possible to make redesign of the project by including state variables to state register. The transformation algorithm contains phases of state splitting, transition splitting, unreachable (dead) state reduction and equivalent states minimization. The results of such transformation can be used for design analysis, optimization, validation, verification, synthesis and implementation. This paper was motivated by author’s work in the project ASFTest – a testbench generator for Aldec finite state machines. Graphical user interface used in state-of-the-art software allows to create environment for design entry with finite state machine abstract usage. Such form of design description is used in many software and hardware design tools like StatedCAD, FPGA Advantage, Stateworks, Stateflows, etc. The algorithm is described in the graphical way using the extended FSM notation. VHDL is chosen as target language. Synthesis is made by Xilinx synthesis tool which is included in Xilinx Webpack environment. The target device is CPLD Coollrunner II.