Перегляд за автором "Karasyov, A."

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  • Зображення мініатюри
    Публікація
    Path Sensitization at Functional Verification of HDL-Models
    (EWDTW, 2006) Shkil, A. S.; Syrevitch, Ye.; Karasyov, A.; Cheglikov, D.
    Strategy of verification of digital devices models, represented in hardware description languages, is considered. The basic idea is in using path sensitization method in a graph model, generating distinguishing tests for separate functional elements, superposing these tests and interactive calculating etalon reactions. The necessity of researches in the field of verification is caused by the lack of effective methods and tools of functional verification of digital devices (DD) models on a step of describing them on behavioral level. World companies – vendors of digital circuits, are forced to decrease their time-to-market. According to vendors’ evaluations, verification (functional as well) takes up to 80% of labor expenditures in the design cycle. There is a big demand for tools of functional verification of devices models on a step of their description in hardware description language (HDL) on behavioral level. If model description in hardware description languages (HDL) is considered as a software program, then, from one point of view it is necessary to execute software verification, but the other point of view it is not always optimal. Software verification considers all modes with all data testing. While checking correspondence between code, which describes a device, and its specification on all possible data for all reachable inputs, to hold on verification during appropriate time with 100% completeness it is not possible. Assume that all in-build operators are combinational elements. It means that to check them it is necessary to drive 2n values, where n – total dimension of inputs. To get high quality of verification for appropriate time it is necessary to decrease number of driven tests. Despite variety of publications, connected with verification and diagnostics of digital devices, today instrumental tools of automatic test generation for complex DD functional verification are actual and claimed. Lack of automatic test generators is felt in many well-known companies: Aldec, Altera, Actel, Xilinx, Synopsis. Thus, this work aim is to develop HDL-models verification strategy, which allows decreasing time on design cycle by decreasing number of test vectors.
  • Зображення мініатюри
    Публікація
    The Method of Fault Backtracing for HDL - Model Errors Searching
    (EWDTS, 2009) Kucherenko, D. E.; Karasyov, A.; Syrevitch, Ye.
    In this paper the method of design error searching in non-structured HDL-code was considered. The method of backtracing was developed. An experiment on HDLmodel of digital device using this method was carried out. In modern CAD tools the basic way of device description is usage of hardware description languages, i.e. VHDL or Verilog, which allow making SOC design process faster. World companies – vendors of digital circuits, are forced to decrease their time-tomarket. Verification of digital projects, that is hardware or built-in hardware-software systems described in a Hardware Description Language - HDL, is the important task during designing digital devices. Often more than 70% of development time is spent on search and correction of mistakes in the project. Process of diagnosing is based on: DD model, allowing carrying out tests generation; designing errors, characteristic for HDL-models; algorithm of tests generation; methods of design errors search. Within the framework of technical diagnostics methods, there are several algorithms of defects search: based on available tests and known function of the device (functional algorithms on the base of errors tables or functions of errors tables), and based on the structure of the device (structural algorithms on the base of a reachability matrix). The purpose of the given work is to develop methods of defects/errors search in a non-structured HDL-code, allowing to reduce time of carrying out of diagnostic experiment and to reduce length of the diagnosis. Proceeding from the aforesaid, it is necessary to solve a task of adaptation of the method of backtracing at verification of HDL-models and to carry out diagnostic experiments on defect/design error search within the framework of verification.