ElAr :: Перегляд за автором "Hahanov, V."

Перегляд за автором "Hahanov, V."

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A Security Model of Individual Cyberspace
(EWDTS, 2011) Adamov, A.; Hahanov, V.
Previous studies in the field of cyberspace security were mostly based on an analysis of a computer network state and identifying vulnerabilities in it [1], or using as security criterion multi-perspective parameters to assess and predict a security state of a network system [2]. In later studies, this approach has been recognized as untenable because it ignores the behaviour of a user when a system anomaly occurs. According to [3] cyberspace is defined as "a massive socio technical system of systems, with a significant component being the humans involved". Thus, the authors attribute the cyber attacks with social, political, economic and cultural phenomena. Today an individual virtual space expanded by the widespread expansion of social networking and Internet services that allow process and store data in the cloud. Thus, users are becoming less tied to their personal digital device, which is only used for access to online services to obtain the necessary data and perform operations. This approach allows us to abstract from hardware characteristics accessing the Internet and use any mobile hardware and software platform for a wide range of tasks in the "cloud" [4]. The examples of such services are cloud office (Google Documents, Microsoft Office Live), sharing of files and images, map services, interpreters, calendars, and, finally, social networks, where each member of a network can store personal information and gain access to multimedia content of other users. All these are evidence of humanity's transition to cloud technology everywhere. The protection of cloud services is hot topic today because these technologies are widely used by organizations to create a business service infrastructure. Accordingly, it is necessary to guarantee the security of corporate data in the cloud, which is an elusive task. Solving this task a company may sign Service Level Agreement (SLA) with a service provider, where all security issues are determined at different levels of representation [5]. For instance, Intel has developed a suite of solutions for secure access and data storage in the cloud. Intel's technologies are supported by leading antivirus companies Symantec and McAfee [6]. Taking in consideration the existing technologies in this area a new model of ICS protection is suggested, which implies the creation of a secure environment for data storage and processing with the help of a cloud computing technology.
Algebra-Logical Repair Method for FPGA Logic Blocks
(EWDTS, 2009) Hahanov, V.; Galagan, S.; Olchovoy, V.; Priymak, A.
At present there are many scientific publications, which cover SoC/SiP testing, diagnosis and repair problems [1-16, 19-20]. The testing and repair problem for the digital system logic components has a special place, because repair of faulty logic blocks is technologically complicated problem. Existing solutions, which are proposed in published works, can be divided on the following groups: 1. Duplication of logic elements or chip regions to double hardware realization of functionality. When faulty element is detected switching to faultless component by means of a multiplexer is carried out [4]. The FPGA models, proposed by Xilinx, can be applied for repair of Altera FPGA components. At repair the main unit of measure is row or column. 2. Application of genetic algorithms for diagnosis and repair on the basis of off-line FPGA reconfiguration not using external control devices [5]. The fault diagnosis reliability is 99%, repair time is 36 msec instead of 660 sec, required for standard configuration of a project. 3. Time-critical FPGA repairing by means of replacement of local CLBs by redundant spares is proposed in [6,7]. In critically important applications the acceptable integration level for CLB replacement is about 1000 logic blocks. The repair technologies for digital system logic, implemented on-chip FPGA, are based on existence or introduction of LUT redundancy after place and route procedure execution. Physical faults, which appear in the process of fabrication or operation, become apparent as logical or temporary failure and result in malfunction of a digital system. Faults are tied not only to the gates or LUT components but also to a specified location on a chip. The idea of digital system repairing comes to the removal of a fault element by means of repeated place and route executing after diagnosis. At that two repair technologies are possible: 1) Blockage of a defective area by means of developing the control scripts for long time place and route procedure. But it is not always acceptable for real time digital systems. The approach is oriented to remove the defective areas of any multiplicity. Blockage of the defective areas by means of repeated place and route executing results in repair of a digital system. 2) Place and route executing for repairing of real time digital systems can result in disastrous effects. The technological approach is necessary that allows repairing of the digital system functionality for milliseconds, required for reprogramming FPGA by new bitstream to remove defective areas from chip functionality. The approach is based on preliminary generation of all possible bitstreams for blocking future defective areas by means of their logical relocation to the redundant nonfunctional chip area. The larger a spare area the less a number of bitstreams, which can be generated a priori. Concerning multiple faults, not covered by a spare area, it is necessary to segment a digital project by its decomposition on disjoin parts, which have their own Place and Route maps. In this case a digital system that has n spare segments for n distributed faults can be repaired. The total chip area consists of (n+m) equal parts. The research objective is to develop a repair method for FPGA logic blocks on the basis of using the redundant chip area. Problems: 1) Development of an algebra-logical repair method for logic blocks of a digital system on basis of FPGA. 2) Development of a method for logic blocks matrix traversal to cover FPGA faulty components by spare tiles. 3) Analysis of practical results and future research.
Assertion Based Method of Functional Defects for Diagnosing and Testing Multimedia Devices
(EWDTS, 2012) Hahanov, V.; Mostova, K.; Paschenko, O.
Essential increase of consumer requirements for complex electronic devices leads to substantial growth of complexity for HW and SW components, services, and system interfaces. Such tendency increases the importance to provide high quality for HW, SW, and networking components and services. Well known rule of ten for hardware components stating that fault detection cost increases in ten times on the next following design or manufacturing stages. The same rule is effectively applicable for Software design stages.One of the main goals which comes to the foreground of industry is to decrease the cost of exploitation by creating the standardized infrastructures for maintenance which providing service exploitation, testing, disposal and, elimination of functional defects. Nowadays fast growing complexities of hardware is transforming this rule into rule of twenty which makes even more important to detect the fault on early design stages, rather then on chip/PCB manufacturing, or system assembling stages [1]. Goal of this work is to develop method which increases product quality by means of developing sufficient HW/SW test and diagnosis approach, also decreasing faults detection and defects localization time in order to improve system performance on example of multimedia devices.
Brain-Like Computer Structures
(ХНУРЭ, 2009) Hahanov, V.; Chumachenko, S. V.; Umerah, N. C.; Yves, T.
High-speed multiprocessor architecture for brain-like analyzing information represented in analytic, graph- and table forms of associative relations to search, recognize and make a decision in n-dimensional vector discrete space is offered. Vector-logical process models of actual applications, where the quality of solution is estimated by the proposed integral non-arithmetical metric of the interaction between binary vectors, are described.
Cyber Physical Social Systems – Future of Ukraine
(EWDTS, 2014) Hahanov, V.; Gharibi, W.; Kudin, A. P.; Hahanov, I.; Ngene, C.; Yeve, T.; Krulevska, D.; Yerchenko, A.; Mishchenko, A.; Shcherbin, D.; Priymak, A.
A fundamental solution of topical problem for economic, social and technological future of Ukraine and the world is proposed. The problem lies in the elimination of corruption through the formation and implementation of the state program «Creation of Cyber Physical Space for Digital Monitoring Technological Processes and Optimal Resource Management in order to Achieve Socially Important Goals». The cyber technology for human-free managing social resources (staff and finance) includes two cloud service: 1) the distribution of government contracts and finance between the structures, undertakings and entities, based on competition of their competence matrices for a given metric; 2) allocation of staff vacancies in scalable social groups based on competition of the competence matrices of applicants for a given metric. The competence metric is a measuring method of the distance between objects or processes based on the use of the parameter vector that defines the space or a competence matrix of a person or social group in real time. A competence matrix is a model of integrated activity and skills of a person or social group at a given metric and time interval. As an alternative solution of the problem it is considered a cyber physical system for managing human and financial resources (Cyber Social Systems - CSS), as a scalable cloud service, available to the social groups, government agencies, private companies and private individuals; it provides lifelong monitoring competencies of corresponding subjects in real time in order to carry out cyber staff management through appropriate career, moral and material incentives according to the results of their constructive activity. The cyber social system is focused on the total destruction of the corruption in the actions of managers at all levels by eliminating the subjectivity in the management of human and financial resources on the basis of the transfer of the official functions to independent cloud cyber service. The system consists of two interacting components: 1) accumulative monitoring of all kinds of human (social group) activity that generates a competence matrix in realtime; 2) the optimal management through career, moral and material incentives of individuals and social formations based on the analysis and rating of the corresponding competence matrices. A cyber system is based on the use of the following technologies: Big Data, Internet of Things, Smart Everything, parallel virtual processors and focused on serving individuals, government agencies and companies. For each subject two unique metrics of competencies are generated: 1) the gold standard of indexes for each category of professional activity; 2) the current competence matrix of the subjects filled in the process of their life, which are ranked by metrical comparison or evaluation of the results of work with standard or better values.
Cyber-social computing of relationship
(Kharkiv National University of Radio Electronics, 2016) Abdullayev Vugar Hacimahmud; Hahanov, V.; Soklakova, T.; Belova, N.
Descriptor Neural Networks with Arbitrary Characteristic Inde
(ХНУРЭ, 2009) Hahanov, V.; Rutkas, A.
We consider a difference descriptor system and its modeling with the help of a neural network. The corresponding descriptor network is a special connection of dynamic and static neurons. The network configuration is defined by the Weierstrass’s normal form of regular matrix sheaf.
Diagnosis Infrastructure of Software-Hardware Systems
(EWDTS, 2011) Yves T.; Hahanov, V.; Alnahhal O.; Maksimov, M.; Shcherbin, D.; Yudin, D.
This article describes an infrastructure and technologies for diagnosis. A transactional graph model and method for diagnosis of digital system-on-chip are developed. They are focused to considerable decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations in the form of test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multitree of fault detection tables, as well as ternary matrices for activating functional components in tests, relative to the selected set of monitors; development of a method for analyzing the activation matrix to detect the faults with given depth and synthesizing logic functions for subsequent embedded hardware fault diagnosing.
Discovering New Indicators for Botnet Traffic Detection
(EWDTS, 2014) Adamov, A.; Hahanov, V.; Carlsson, A.
Botnets became the powerful cyber weapon that involves tens of millions of infected computers – “cyber zombies” – all over the world. The security industry makes efforts to prevent spreading botnets and compromising an Individual Cyberspace (IC)[1] of users in such way. However, botnets continue existing despite numerous takedowns initiated by antivirus companies, Microsoft, FBI, Europol and others. In this paper we investigate existed methods of traffic detection represented mostly by IDS system and discover new indicators that can be utilized for improving botnet traffic detection. To do this we analyse the most prevalent backdoors communication protocols that stay behind of the popular botnets. As a result, we extracted new data that might be used in detection routines of IDS (Intrusion Detection System). An objective of the study is mining new indicators of compromise from botnet traffic and using them to identify cyber-attacks on IC. The analysis method assumes analysis of a communication protocol of the top botnet backdoors. The discovered results that can be used to improve detection of infected hosts in a local network are presented in this paper. A modern society sees an increase in cyber attacks that is attempted to be mitigated by antivirus and other security companies. Nowadays an Individual Cyberspace is highly vulnerable against identity and money theft on the Internet. The most spread and dangerous threat for every Internet user is botnets that conquer more and more user computers and turning them into “cyber zombies”. Despite numerous takedown attempts the botnets are still alive and continue successfully stealing users’ credentials. Detecting botnet is a complex task because of two major reasons: using encryption for transferred data, involving numerous infected bots as proxy layers to deliver data to C&C. Currently the botnets became an unbreakable despite of recent takedowns of Kelihos and Zeus botnets because of distributed nature of botnets and using several layers of proxy-bots. The latest Tovar Operation jointly run by FBI, NCA, Europol and antivirus companies in the beginning of June disconnected Zeus bots from mothership C&C(Command and Control) servers.
Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints
(EWDTW, 2006) Zaychenko, S.; Hahanov, V.; Zaharchenko, O.
Today the Assertions Based Verification (ABV) is by all means the most effective verification technology for SoC designs. Assertions provide basic blocks for building functional verification concept. Assertions simply catch a lot of design errors on early phases. This paper suggests new effective algorithmic model for assertions checking within the testbench-based simulation. The algorithms for handling key temporal operators from Property Specification Language (PSL) are described. Paper demonstrates the advantages of the suggested model over existing equivalents - in simulation performance, verification efficiency and model extensibility. Obviously, the verification process is a very complex and a very expensive part of the modern SoC design cycle. This process consists of searching the model for mistakes, causing the design to violate the functional specification, localizing the problems reasons and applying the fixtures. According to the EDA industry experts opinion, the cost of verification in ASIC [1] designs often overheads the 70% of the entire project budget [2]. Such high cost of the system quality is driven by several factors, in particular: – A large amount of missed details and mistakes in the work of SoC designers in the RTL code, verification engineers mistakes in the testbenches, also, the inevitable ambiguities of the original design specification; – drawbacks in the choosen design flows, complicating the bugs localization and fixtures, missing the possibilities for early discovery of the typical problems; – relatively low performance and bugs within the selected automation tools, which reach the quality and performance goals much slower than the input design complexity raises. Resolving these problems altogether and degrading the SoC verification cycle cost is currently a primary goal for the entire EDA world [3]. Leading EDA companies and industry experts are focused on developing the new generation of complex design verification methods, which will be able to: – minimize the human participation in the routine design and verification procedures, which will obviously decrease the probability of mistakes in several times; – lead to catching the largest amount of problems on the early design phases, reducing the average fixture cost; – upgrade the performance and stability of the design verification systems by raising the abstraction level both for the SoC models and for the testing stimulus. There are two basic directions in modern SoC verification methods – dynamic methods [2,4], based on the simulation, and static, or formal methods [5,6], based on the mathematical proof of certain system properties without testing stimulus. There are also hybrid methods [7] used, which assume usage of the simulation and functional coverage results to improve the performance of formal methods. This work is focused on the assertions-based verification technology [8,9], playing its role both in dynamic and formal methods.
Method for Diagnosing SoC HDL-code
(EWDTS, 2014) Zaychenko, S.; Hahanov, V.; Varchenko, V.
This article describes technology for diagnosis SoC HDL-models, based on Code-Flow Transaction Graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis. The goal is creation TAB-matrix model (Tests – Assertions – Blocks functional) model and diagnosis method to decrease the time of testing and memory for storage by means of forming ternary relations (test – monitor – functional component) in a single table. The problems are: 1) development of digital system HDL-model in the form of a transaction graph for diagnosing functional blocks by using assertion set; 2) development method for analyzing TABmatrix to detect minimal set of fault blocks; 3) Synthesis of logic functions for embedded fault diagnosis procedure.
Metrics of Vector Logic Algebra for Cyber Space
(ХНУРЭ, 2011) Hahanov, V.; Chumachenko, S. V.; Mostovaya, K.
The algebraic structure determining the vectormatrix transformation in the discrete vector Boolean space for the analyzing information based on logical operations on associative data.
Optic Link System
(ХНУРЭ, 2009) Filippenko, I. O.; Hahanov, V.
In given article is overviewed the digital optic link system and the problem of encoding analog information in communication systems. This system can be used as warless computer networking with out paying for radio band. As optic transmitter used red semiconductor laser.
Security Risks and Modern Cyber Security Technologies for Corporate Networks
(ХНУРЭ, 2010) Adamov, A.; Hahanov, V.; Gharibi, W.
The article aims to highlight current trends on he market of corporate antivirus solutions. Brief overview of modern security threats that can destroy IT environment is rovided as well as a typical structure and features of ntivirus suits for corporate users presented on the market. he general requirements for corporate products are etermined according to the last report from avomparatives.org [1]. The detailed analysis of new features is rovided based on an overview of products available on the market nowadays. At the end, an enumeration of modern trends in antivirus industry for corporate users completes this rticle. Finally, the main goal of this article is to stress an ttention about new trends suggested by AV vendors in their olutions in order to protect customers against newest security hreats.
Testing and Verification of HDL-models for SoC components
(EWDTS, 2009) Hahanova, I. V.; Hahanov, V.; Ngene, C. U.; Yves, T.
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-tomarket) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed. The novel testing and verification technology for system HDL models allows searching for errors in the HDL-code with a given thoroughness for an acceptable time by means of the introduction assertion redundancy to the critical points of the software model, which are defined by the synthesized logic functions of the testability. The controllability and observability criteria, used in hardware design and test, are applied to estimate the quality of software code in order to improve it and effective diagnose semantic errors. The objective is improvement of the testing and verification technology for digital systems to diagnose and correct of errors for HDL-models by sharing of the assertion engine and testable design technologies. The research tasks: 1. Design verification and testing environment for system HDL-model on the basis of assertions. 2. Development of testability evaluation metrics on the basis of new logic testability function. 3. Application of a technological assertion model to verify an IP-core filter on the basis of discrete cosine transform. 4. Practical results and directions for further research. The research sources: 1. Technologies and tools of test and testbench creation are represented in the papers [1-3]. 2. Models and methods for verification of the system models on the basis of assertions are described in [4-7]. Testable software design uses the IEEE standards [8-10], as well as innovative solutions to verify and testability analysis for the system HDLmodels [11-18].

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