Перегляд за автором "Gorobets, A."

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  • Зображення мініатюри
    Публікація
    System in Package. Diagnosis and Embedded Repair
    (EWDTS, 2009) Hahanov, V. I.; Sushanov, A.; Stepanova, Y.; Gorobets, A.
    Problems of System in Package (SiP), as new constructive generation, modules testing are considered. The method of digital system diagnosis based on the disjunctive normal form, which is represented by fault coverage matrix of test sequences are proposed. The method is focused on embedded service functionality, presented as F –IP modules. Methods for embedded functionality repair are adapted. New Technology System in Package actively gaining market of microelectronics. This technology provides a more complete functional and small board size. Such system in the package contains 2 or more crystals, which are combined with passive components, filters and other components. As a rule, highly derived product used in a specific device for solving pre-defined tasks. Using SiP has significant advantages over other technologies, such as: increasing the productivity of digital systems, miniaturization of the volume, product weight reducing, reducing delay of signals propagation, power and cost of confirmed device. But, like any other technology, the development of SiP has negative characteristics, among which are: the hardware complexity of digital systems in a package, which has had billions of valves and hundreds of millions of transistors on a single crystal, the high cost of design, low output suitable products SiP , the technological complexity of recovery, the limited market-design problem of heat from hot components are added to the problem and the developers of devices, such as: testing of wafers, substrates, functional modules. problems of silicon crystals joining in the digital electronic system, mechanical protection of internally silicon crystals, assembly, heat dissipation have not been decided (Fig.1). By the above-mentioned problems of testing, test of logic should be added. The memory diagnosis and repair problem is related to the tendency to continuous reduction of chip area, which is allocated to original and standardize logic, and simultaneous growth of embedded memory. Figure shows increasing of the memory specific weight on a chip, which will reach 94% by 2014 year. It will provide not only fast response of carrying out of functions, but also flexibility that is appropriate to software in relation to design error correction.
  • Зображення мініатюри
    Публікація
    Testing Challenges of SOC Hardware-Software Components
    (EWDTS, 2008) Hahanov, V. I.; Obrizan, V.; Miroshnichenko, S.; Gorobets, A.
    Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. Adaptation of testing and verification methods of digital systems can bring in big financial and time dividends, when using for testable design and diagnosis of software. Consideration of the following questions can be interesting: 1. Classification of key uses of SoC testable design technologies in software testing and verification problems. 2. Universal model of hardware and software component in the form of directed register transfer and control graph, on which the testable design, test synthesis and analysis problems can be solved. 3. Metrics of testability (controllability and observability) evaluation for hardware and software by the graph register transfer and control model. The silicon chip that is basis of computers and communicators development has to be considered as the initiate kernel of new testing and verification technologies appearance in software and computer engineering. A chip is used as test area for new facilities and methods creation and testing for component routing, placement, synthesis and analysis. Technological solutions, tested by time in microelectronics, then are captured and implemented into macroelectronics (computer systems and networks). Here are some of artifacts, relating to the continuity of technological innovations development