Перегляд за автором "Galagan, S."

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  • Зображення мініатюри
    Публікація
    Algebra-Logical Repair Method for FPGA Logic Blocks
    (EWDTS, 2009) Hahanov, V.; Galagan, S.; Olchovoy, V.; Priymak, A.
    At present there are many scientific publications, which cover SoC/SiP testing, diagnosis and repair problems [1-16, 19-20]. The testing and repair problem for the digital system logic components has a special place, because repair of faulty logic blocks is technologically complicated problem. Existing solutions, which are proposed in published works, can be divided on the following groups: 1. Duplication of logic elements or chip regions to double hardware realization of functionality. When faulty element is detected switching to faultless component by means of a multiplexer is carried out [4]. The FPGA models, proposed by Xilinx, can be applied for repair of Altera FPGA components. At repair the main unit of measure is row or column. 2. Application of genetic algorithms for diagnosis and repair on the basis of off-line FPGA reconfiguration not using external control devices [5]. The fault diagnosis reliability is 99%, repair time is 36 msec instead of 660 sec, required for standard configuration of a project. 3. Time-critical FPGA repairing by means of replacement of local CLBs by redundant spares is proposed in [6,7]. In critically important applications the acceptable integration level for CLB replacement is about 1000 logic blocks. The repair technologies for digital system logic, implemented on-chip FPGA, are based on existence or introduction of LUT redundancy after place and route procedure execution. Physical faults, which appear in the process of fabrication or operation, become apparent as logical or temporary failure and result in malfunction of a digital system. Faults are tied not only to the gates or LUT components but also to a specified location on a chip. The idea of digital system repairing comes to the removal of a fault element by means of repeated place and route executing after diagnosis. At that two repair technologies are possible: 1) Blockage of a defective area by means of developing the control scripts for long time place and route procedure. But it is not always acceptable for real time digital systems. The approach is oriented to remove the defective areas of any multiplicity. Blockage of the defective areas by means of repeated place and route executing results in repair of a digital system. 2) Place and route executing for repairing of real time digital systems can result in disastrous effects. The technological approach is necessary that allows repairing of the digital system functionality for milliseconds, required for reprogramming FPGA by new bitstream to remove defective areas from chip functionality. The approach is based on preliminary generation of all possible bitstreams for blocking future defective areas by means of their logical relocation to the redundant nonfunctional chip area. The larger a spare area the less a number of bitstreams, which can be generated a priori. Concerning multiple faults, not covered by a spare area, it is necessary to segment a digital project by its decomposition on disjoin parts, which have their own Place and Route maps. In this case a digital system that has n spare segments for n distributed faults can be repaired. The total chip area consists of (n+m) equal parts. The research objective is to develop a repair method for FPGA logic blocks on the basis of using the redundant chip area. Problems: 1) Development of an algebra-logical repair method for logic blocks of a digital system on basis of FPGA. 2) Development of a method for logic blocks matrix traversal to cover FPGA faulty components by spare tiles. 3) Analysis of practical results and future research.
  • Зображення мініатюри
    Публікація
    Diagnosis of SoC Memory Faulty Cells for Embedded Repair
    (EWDTS, 2008) Litvinova, E. I.; Hahanov, V. I.; Krasnoyaruzhskaya, K.; Galagan, S.
    A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It enables to obtain minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in the form of memory rows and columns. Modern digital systems-on-chip (SoC) include millions of equivalent gates and new high-level design technologies are necessary for their creation [1-3]. SoC memory in the future will occupy more than 90% of chip area that is oriented on use flexible software [3- 7,11]. Development of models and methods of quick and exact diagnosis, as well as technologies for repair of faulty cells by on-chip facility in real time and on all life cycle stages of a product are urgent problems. It will enable to decrease quantity of chip pins, to raise yield, to decrease time-to-market, to reduce service costs, as well as to remove output diagnosis and repair facility [1,6,7,12]. The research aim is development of algebra-logical method of embedded matrix memory diagnosis and repair in real time. The problems: 1) Analysis of SoC Infrastructure Intellectual Property Technologies; 2) Development of an Infrastructure Intellectual Property method on basis of the covering matrix; 3) Formalization of the algebralogical AL-method for embedded memory repair; 4) Analysis of obtained results. Modern design technologies of digital systems on chips propose along with creation of functional blocks F-IP development of service modules I-IP, which are oriented on complex solving of the project quality problem and yield increasing in manufacturing that is determined by implementation of the following services into a chip [11,14,16]: 1) Diagnosis of failures and faults by analysis of information, which is obtained on the stage of testing and use of special methods of embedded fault lookup on basis of the standard IEEE 1500 [8,13,15]; 2) Repair of functional modules and memory after fixation of a negative testing result, fault location and identification of a fault type in carrying out of the diagnosis phase; 3) Measurement of the general characteristics and parameters of a device operation on basis of on-chip facilities, which enable to make time and volt-ampere measurements; 4) Reliability and fault tolerance of a device operation in working that is obtained by diversification of functional blocks, redundancy of them and repair of SoC in real time.
  • Зображення мініатюри
    Публікація
    Verification and Diagnosis of SoC HDL-code
    (EWDTS, 2011) Hahanov, V. I.; Park, Dong Won; Guz, O. A.; Galagan, S.; Priymak, A.
    Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertionbased models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered. Recent trends in creating new communications, computing and information services, useful to the human, are development of dedicated gadgets, which have important advantages over PCs and laptops: power consumption, compactness, weight, cost, functionality, and friendliness of interface. Practically the top ten dedicated products 2010 (Apple iPad, Samsung Galaxy S, Apple MacBook Air, Logitech Revue, Google Nexus One (HTC Desire), Apple iPhone 4, Apple TV, Toshiba Libretto W100, Microsoft Kinect, Nook Color) is realized as digital systems-on-chips. By 2012 the mobile and wireless communication market will move to 20 nm (results of the January 2011 Technology Forum of Common Platform Alliance). Further development of the technologies by year: 2014 – 14 nm, 2016 – 11 nm. In 2015 more than 55% of mobile phones will be smartphones, tablet PCs will replace laptops and netbooks. Superfones (Nexus-1, Google) will unite all devices and services. The transition from the computing platform to mobile devices with small size results in considerable reduction in power consumption worldwide. The next computerization wave, entitled "Internet of things", is being accelerated. It will lead to widespread sensor networks, including their integration into the human body. The world market of the above devices and gadgets today involves about 3 billion products. For their effective designing, manufacturing and exploitation the new technologies and Infrastructures IP are created.