ElAr :: Перегляд за автором "Chumachenko, S. V."

Перегляд за автором "Chumachenko, S. V."

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Brain-Like Computer Structures
(ХНУРЭ, 2009) Hahanov, V.; Chumachenko, S. V.; Umerah, N. C.; Yves, T.
High-speed multiprocessor architecture for brain-like analyzing information represented in analytic, graph- and table forms of associative relations to search, recognize and make a decision in n-dimensional vector discrete space is offered. Vector-logical process models of actual applications, where the quality of solution is estimated by the proposed integral non-arithmetical metric of the interaction between binary vectors, are described.
Cyber Physical System – Smart Cloud Traffic Control
(EWDTS, 2014) Hahanov, V. I.; Wajeb Gharibi; Abramova, L. S.; Chumachenko, S. V.; Litvinova, E. I.; Hahanova, A. V.; Rustinov, V.; Miz, V.; Zhalilo, A.; Ziarmand, A.
A cyber physical system for smart cloud traffic control is proposed. It is an intellectual (smart) road infrastructure for monitoring and control of traffic in real-time through the use of global systems for positioning and navigation, mobile gadgets and the Internet in order to improve the quality and safety of vehicle movement, as well as for minimizing the time and costs when vehicles are moved at the specified routes. The main innovative idea is step-by-step transfer of traffic lights from the ground to a virtual cloud space for vehicle management, equipped with a mobile gadget or computer, which displays on the screen map, route, coordinates of the road user and real traffic signals. A set of innovative technologies to address the social, humanitarian, economic, energy, insurance, crime and environmental problems through the creation and application of cloud-based digital traffic monitoring and management is developed. All of these technologies and functional components are integrated into the system automaton model of cyber physical system for interaction between an infrastructure cloud of exact monitoring and digital control and vehicle gadget or computer.
Design and Optimization of a Planar UWB Antenna
(EWDTS, 2013) Lim, Eng Gee; Wang, Zhao; Juans, Gerry; Man, Ka Lok; Zhang, Nan; Hahanov, V. I.; Litvinova, E. I.; Chumachenko, S. V.; Mishchenko, A.; Dementiev, S.
In this paper, we present our design on a simple, low-profile wideband planar antenna with a pure circular radiator fed by a 50 Ω microstrip line. By investigating the feeding position and ground plane dimensions, the antenna is optimized to have a very wide bandwidth that covers the whole FCC-allocated ultra-wideband (UWB) spectrum. Because of the additional patch beneath the radiator, the bandwidth can be further extended towards the lower side of the frequency spectrum. This antenna is finally modified to have a bandwidth from 2 to 12 GHz, which satisfies system requirements for S-DMB, WiBro, WLAN, CMMB and the entire UWB with S11 < -10dB. Since the Federal Communications Commission (FCC) of United States allocated the unlicensed frequency spectrum from 3.1 GHz to 10.6 GHz for commercial applications of ultra-wideband (UWB) technology in 2002 [1], ultra-wideband (UWB) technology has gained great popularity in research and industrial areas because of its high data rate wireless communication capability for various applications. As a crucial part of the UWB system, UWB antennas have been investigated extensively by researchers and numerous proposals for UWB antenna designs have been reported [2-5]. In [2], a new ultra-wideband antenna consisting of two steps, a single slotted patch and a partial ground plane is designed to operate from 3.2 to 12 GHz. In J. N. Lee’s work [3], an ultrawideband antenna composed of a modified trapezoidal radiating patch, a PI-shaped matching stub, CPW feeding, and two steps for impedance matching has been proposed for UWB applications. In [4], an ultrawideband microstrip-fed monopole antenna with a narrow slit and a modified inverted U-slot on the patch is presented. Recently, a small planar antenna fed by a microstrip line has been investigated and designed to exhibit dualband operation for Bluetooth (2.4 - 2.484 GHz) and UWB (3.1 - 10.6 GHz) bands [5]. However, many of the proposed designs employed slots or other complicated modifications in the antenna radiator and/or ground plane. These designs may pose complications during fabrication of the antenna since the tolerance of the increased special features/variables could be problematic when it goes to mass production, and instability due to the fact that complicated antenna structures may also occur in practice. Therefore, we are motivated to design a low complexity, low cost and compact antenna with wide frequency coverage supporting various applications such as Satellite Digital Multimedia Broadcasting (S-DMB), Wireless Broadband (WiBro), Wireless Local Area Network (WLAN), China Multimedia Mobile Broadcasting (CMMB) and UWB. In this paper, we present a very simple circular planar antenna with operating bandwidth ranging from 2 GHz to 12 GHz by integrating several techniques into one compact antenna. The design approach is very similar to our previously reported paper [6]. We start with a simple circular planar antenna fed by a 50Ω microstrip line with a truncated ground plane. Next, based on the study of the size of the radiator and current distribution, the antenna is designed to have an operating bandwidth covering the entire UWB band, i.e. 3.1 - 10.6 GHz. Then, the study on the size of the partial ground plane is conducted to increase the bandwidth towards the lower side of the frequency spectrum, to cover the bands for WLAN (2.4 - 2.484 GHz) and CMMB (2.635 – 2.66 GHz). With an extra patch printed on the back side of the substrate, underneath the circular radiator, the bandwidth can be further increased to cover Wibro (2.3 - 2.4 GHz) and S-DBM (2.17 -2.2 GHz) without significantly influencing other frequency bands. Thus the proposed antenna can be used for various applications such as SDMB, Wibro, WLAN, CMMB and the operating bands are evaluated using with the criterion of having return loss S11 less than 10 dB. Simulated radiation patterns over the whole frequency bands are acceptable.
Metrics of Vector Logic Algebra for Cyber Space
(ХНУРЭ, 2011) Hahanov, V.; Chumachenko, S. V.; Mostovaya, K.
The algebraic structure determining the vectormatrix transformation in the discrete vector Boolean space for the analyzing information based on logical operations on associative data.
Models and Methods for Verification and Diagnosis of SoC HDL-code
(ХНУРЭ, 2010) Hahanov, V. I.; Gharibi, W.; Litvinova, E. I.; Chumachenko, S. V.
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.
Models for Quality Analysis of Computer Structures
(EWDTS, 2012) Murad, Ali Abbas; Chumachenko, S. V.; Hahanova, A. V.; Gorobets, A. A.; Priymak, A.
The methods for estimating computational structures and searching the shortest paths between the pair of nodes are presented. A criterion for evaluating the effectiveness of computational structures based on the graph model of the functional blocks of digital systems-on-chips is developed. A modified Dijkstra's algorithm to determine the average cost of interconnections in computing architecture for every pair of nodes is proposed. Verification of the criterion, when evaluating the effectiveness of different topologies of computational structures is performed. Creating effective computational structures is related not only to increasing the speed of primitives, but also with the topology of interconnections between them, which can significantly improve the performance of parallel processing data due to additional expensive connections. It is therefore necessary to have criteria for evaluating performance, taking into account not only transaction time between the nodes, but the hardware redundancy, which considerably reduces the average time of receiving and transmission of information between the primitive computing components. Such criteria can be used to evaluate the effectiveness of graph models of local and global computer networks, urban infrastructure of road communications, as well as the traffic flows in order to identify bottlenecks affecting the traffic. The problem of finding such criteria is related to the minimization of the computational cost for determination of all possible minimal paths between nodes of pairs. The aim of research is development of criteria for evaluating the effectiveness of computational structures, based on graph model of interconnections of functional blocks, which make it possible to determine the quality of the topological architectures of digital systems-on-chips. The objectives: 1) Analysis of methods for estimating the computational structures and finding the shortest paths between nodes of pair. 2) Development of criteria for evaluating the effectiveness of computational structures, based on graph model of the functional blocks of digital systems-on-chips. 3) Modification of Dijkstra's algorithm to determine the average cost of interconnections of computing architecture for a node pair. 4) Verification of the criteria when evaluating the effectiveness of different topologies of computational structures.
Quantum data structures for SoC design
(2015) Chumachenko, S. V.; Shkil, A. S.; Hahanova, A. V.; Ziarmand, A. N.; Pryimak, A.
A qubit-vector model of computing automaton is proposed; it is characterized by the transactional interaction of memory components, which represent the combinational and sequential elements and are implemented in the form of a qubit or “quantum” primitives needed to create parallel virtual computers and cloud-focused processors.
Qubit Minimization of Boolean Functions
(Харьковский национальный университет радиоэлектроники, 2018) Hahanov, V. I.; Ka Lok Man; Liubarskyi, Mykhailo; Hahanov, I.; Chumachenko, S. V.
The memory-driven innovative architecture of logic-free quantum computing is presented, which is characterized by the use of photon read-write transactions in the structure of electrons associated with superposition and entanglement of states. The quantum methods for parallel minimization of Boolean functions and solving the coverage problem based on the use of qubit data structures are proposed.
Qubit Model for Solving the Coverage Problem
(EWDTS, 2012) Hahanov, V. I.; Litvinova, E. I.; Chumachenko, S. V.; Baghdadi, Ammar Awni Abbas; Eshetie, Abebech Mandefro
Qubit (quantum) structures of data and computational processes for significantly improving performance when solving problems of discrete optimization and fault-tolerant design are proposed. We describe a hardware-focused models for parallel (one cycle) calculating the power set (the set of all subsets) on the universe of n primitives for solving coverage problems, minimization of Boolean functions, data compression, analysis and synthesis of digital systems through the implementation of the processor structure in the form of the Hasse diagram. A prototype of quantum device, implemented by programmable logic, is described. A quantum computer is designed for fault-tolerant design and solving optimization problems by way of the brute-force method through the use of set theory. Considering the discreteness and multiple-valuedness of the alphabets for description of information processes, the parallelism, inherent in the quantum computing, is particularly actual when developing effective and intelligent engines for data retrieval in cyberspace or Internet, tools for synthesis of faulttolerant digital primitives and systems, designing and testing digital systems-on-chips, tools for solving problems of discrete optimization. It does not cover the physical basis of quantum computing, originally planted in the works of scientists, focused on the use of non-deterministic quantum interactions within the atom.
Reproducing kernel hilbert space methods for cad tools
(EWDTW, 2004) Chumachenko, S. V.; Khawar, Parvez; Gowher, Malik
The review of known RKHS-methods for analysis of current state in science investigations is represented. The place of Series Summation Method in Reproducing Kernel Hilbert Space (RKHS) is determined. The new results obtained by this method are discussed. Reproducing Kernel Hilbert Space (RKHS) methods are interesting both pure theoretically and applied. RKHS theory has been a well studied topic, stemming from the original works of [1] to more recent studies on their application by [2, 3, 8-11]. Mathematical models based on RKHS and causal operators are presented in [3]. They are used at Pattern Recognition [4], Digital Data Processing [5], Image Compression [6], Computer Graphics [7]. Mentioned directions are described by mathematical tool – theory of wavelets [4]. RKHS methods are base tool in exact incremental learning [8], in statistical learning theory [2, 9]. The general theory of reproducing kernels which is combined with linear mappings in the framework of Hilbert spaces is considered in [2]. A framework for discussing the generalization ability of a trained network in the original function space using tools of functional analysis based on RKHS is introduced in [8]. Special kind of kernel based approximation scheme is also closely linked to regularization theory [10] and Support Vector Machines based approximation schemes [11] (Fig.).
SoC Software Components Diagnosis Technology
(EWDTS, 2008) Chumachenko, S. V.; Gharibi, W.; Hahanova, A. V.; Sushanov, A.
A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown. There are technologies of hardware testing and testable design, which enable to solve the problem of SoC service effectively. On the other hand, there are not effective models and methods of the given problem solving on the electronic technology market. To realize testable design and diagnosis of SoC software components the universal model of software components representation in the form of register transfer and control graph is developed. An algorithm of software diagnosis is proposed. An instance of software diagnosis technology utilization is considered. The research aim is adaptation of the hardware testing methods to the service of SoC software components. The research problems: 1) Adaptation of ThatteAbraham-Sharshunov register transfer model to the solving of software testing problem; 2) Application of the model for faulty statements diagnosis on basis of use the fault detection table.
Spam Diagnosis Infrastructure for Individual Cyberspace
(EWDTS, 2011) Hahanov, V. I.; Mischenko, A.; Chumachenko, S. V.; Hahanova, A. V.; Priymak, A.
The theory, methods and the architecture of parallel information's analysis is presented by the form of analytical, graph and table forms of associative relations for the search, recognition, diagnosis of destructive components and the decision making in ndimensional vector cybernetic individual space. Vector -logical processes-models of actual oriented tasks are considered. They include the diagnostic of spam and the recovery of serviceability, the hardwaresoftware components of computer systems and the decision quality is estimated by the interactions of nonarithmetic metrics of Boolean vectors. The concept of self-development information of computer ecosystem is offered. It repeats the evolution of the functionality of the person. Original processes-models of associativelogical information analysis are represented on the basis of high-speed multiprocessor in n-dimensional vector discrete space. The problem of creating an effective infrastructure of cyberspace (Cyber Space), as well as selfdeveloping information and computing ecosystems (ICES) of the planet is particularly important for global companies, such as Kaspersky Laboratory, Google and Microsoft. Cyberspace as an object of nature is also susceptible to destructive components affecting the performance of subjects, which are computers, systems and networks. Therefore, now and in the future it remains as an important problem of space standardization and specialization of all the interacting entities, including the negative, as an integral part of the ecosystem. This action is permanent in time, whose purpose is to keep up, but one step ahead of the emergence of new malicious components, by creating an infrastructure cybernetic space, operating the computer ecosystem of the planet and the quality of each person's life.
SUM IP Core Generator – Means for Verification of Models-Formulas for Series Summation in RKHS
(EWDTW, 2006) Hahanov, V. I.; Chumachenko, S. V.; Skvortsova, Olga; Melnikova, Olga
Program system SUM IP Core Generator – means for verification of models – formulas of series summation in Reproducing Kernel Hilbert Space (RKHS) which allows to carry out input of the description of the model-formula with the help of the GUI-interface is offered; to model models – formulas with the help of software products Mathematica, Sinplify, Modelsim, Riviera, Active HDL; to generate initial files IP-core in languages of the description of equipment VHDL, Verilog, System C; to generate scripts – files for modelling, synthesis, implementation, time modelling; to synthesize tests, parameters, conditions for verification on basis Testbench; to carry out post-synthesis modelling for revealing mistakes in codes. The program system SUM IP Core Generator is proposed. Its structure is represented on Fig. 1. The Purpose of this system is essential reduction of time for data preparation by use of the user-friendly GUI-interface with a view of the subsequent modelling for definition of adequacy and accuracy of modelsformulas, and also automatic generation of the HDLcode considered in quality IP Сore. Solved problems (see fig. 1): 1. Input of the description of the model-formula with the help of the GUI-interface. 2. Modelling models-formulas with the help of software products Mathematica, Sinplify, Modelsim, Riviera, Active HDL. 3. Generation of initial files IP-core in languages of the description of equipment VHDL, Verilog, System C. 4. Generation of scripts-files for modelling, synthesis, implementation, time modelling. 5. Synthesis of tests, parameters, conditions for verification on the basis of generating Testbench. 6. Post-synthesis modelling for revealing mistakes in codes.
Technology for Faulty Blocks Coverage by Spares
(EWDTS, 2009) Hahanov, V. I.; Chumachenko, S. V.; Litvinova, E. I.; Zaharchenko, O.; Kulbakova, N.
The technology for the minimum coverage of faulty blocks by spares when repairing the logic part of digital system-on-chip is proposed. The general provisions and rules of coverage for the matrix of configurable logic blocks (CLB) with faulty cells are considered. Coverage criteria for faulty cells are developed. Examples of the algorithm implementation are made. Billions of digital systems-on-chips, used in the world, containing up to 16 types of various components (processor, memory, logic, buses, dedicated computers), which can be divided into 2 subsets: the memory (90%) and logic (10%). At that faults, detected in memory, are repaired successfully by the onchip facilities of the leading companies (Virage Logic, Intel). But almost 10% of logic is unamenable to regular solutions in the on-chip repair. Today, the world's biggest problem in the market of electronic technology is repairing the logic part of digital system-on-chip. Due to high market appeal the problem of diagnosis and repair of memory and logic cells is considered in the paper. It is one of the Gartner's Top 10 Strategic Technologies for 2009 that is solved by readdressing faulty cells to faultless components from the spare rows, columns and tiles. The strategy works on the logic blocks, which must be addressed (and should be provided with repair blocks) or reprogrammable on the faultless space of the chip for the embedded repair. Repair models for SiP memory modules are considered in the papers [1-6]. It should also take into account that the level of sales of computers has fallen in the 2 quarter of 2009 by 8% and amounted to 66 million pieces, but sale of laptops has grown by 20%. With regard to market of chips, there is the highest rise of sales in the last 13 years. This fact confirms Moore's Law – transistor today is worthless, a user will pay for power. The whole world sees the future of digital systems-on-chips. Conclusion – all market-based ideas will be implemented in the chip with a dedicated functionality. So, Infrastructure IP creation in a chip is important problem, because it is capable to realize the embedded diagnosis and repairing, which will significantly improve the yield and extend the life cycle of digital product. Therefore, any new solution in this area might be interesting for the market of electronic technology, which determines the urgency of the proposed technology for quasi-optimal faulty blocks coverage by spare components. The papers [7-9] are devoted to the development of the theory and methods for optimization of geometric design, in particular, the research of optimization placement problem for rectangular objects. The optimization placement problem for rectangular objects with variable metric characterizations in a given area is considered in [7, 8]. The analysis of advanced technologies for embedded Functional Intellectual Property of digital system-in-package is shown in [10]. Features of the architecture «System-in-Package» and present repair strategies for digital systems-on-chips, as well as the method of evaluation the reliability of their performance are considered. The problem of SoC testing technologies adaptation to new digital system embodiment System-in-Package (SiP) that allows implementing on-chip sophisticated specialty computers and RF devices is considered in [10]. System-in-Package forms new objectives and goals of Infrastructure IP for real time SiP functionality, which differ from embedded SoC diagnosis essentially. Structure-logical diagnosis and repair methods for FPGA functional logic blocks based on real time fault detection table analysis are proposed. A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed in [10]. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The objective of the research is the development of technology for the optimal faulty blocks coverage by spares when repairing the logic of digital SoC. Research tasks are: 1) The development of generalities and rules to cover the matrix of configurable logic blocks with faulty cells. 2) The development of coverage criteria for faulty cells. 3) Flowcharting for the bypassing the matrix of configurable logic blocks to obtain coverage. 4) Flowchart examples.
Testing and Diagnosis of Bad Messages in Individual Cyberspace
(ХНУРЭ, 2012) Hahanov, V. I.; Chumachenko, S. V.; Mischenko, A.
The theory, methods and the architecture of parallel information's analysis is presented by the form of analytical, graph and table forms of associative relations for the search, recognition, diagnosis of destructive components and the decision making in n-dimensional vector cybernetic individual space. Vector-logical processes-models of actual oriented tasks are considered. They include the testing and diagnosis of bad massages and the recovery of serviceability, the hardware-software components of computer systems and the decision quality is estimated by the interactions of non-arithmetic metrics of Boolean vectors. The concept of self-development information of computer ecosystem is offered. It repeats the evolution of the functionality of the person. Original processes-models of associative-logical information analysis are represented on the basis of high-speed multiprocessor in n-dimensional vector discrete space.
Verification and testing RKHS series summation method for modelling radio electronic devices
(EWDTW, 2005) Chumachenko, S. V.; Chugurov, I. N.; Chugurova, V. V.
Reproducing Kernel Hilbert Space (RKHS) for Series Summation that allows analytically obtaining alternative representations for series in the finite form is developed. To increase efficiency of solving of computational tasks there are used mathematical co-processors, which implement most efficient ways of computing equations, integrals, differential coefficients, ets. It is obvious that after discovering of new methods of increasing computation accuracy and decreasing computation time it is necessary to re-implement mathematical coprocessors or use new generation of IP-cores in PLD, Gate Array, ASIC designs. The method of reduction of computation of certain types of series to exact function that is widely used during calculation of parameters of high radio frequency devices was presented in [1-4]. This method decrease computation time of such tasks in tens and hundred times and its inaccuracy is equals to zero. The purpose of the investigation is verification and testing Series Summation Method in RKHS for modelling radio electronic devices.

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