Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/2132
Title: Vector-Logical Diagnosis Method for SOC Functionalities
Authors: Hahanov, Vladimir
Guz, Olesya
Kulbakova, Natalya
Davydov, Maxim
Keywords: Vector-Logical Diagnosis Method
SOC Functionalities
Issue Date: 2008
Publisher: EWDTS
Citation: Hahanov Vladimir Vector-Logical Diagnosis Method for SOC Functionalities /Vladimir Hahanov, Olesya Guz, Natalya Kulbakova, Maxim Davydov //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)
Abstract: Models and methods of vector-logical diagnosis of SoC functionalities in real time are proposed. Algebralogical procedures of embedded fault diagnosis by means of DNF synthesis that forms all functionality diagnosis solutions are described. The method is based on use the fault detection table that is result of fault simulation. The research aim is development of embedded diagnostic service method of digital system-on-a-chip functionalities that is intended for faulty SoC component detection in real time. The problems: 1) The state of the SoC I-IP market technology [1-5]; 2) Vector-logical (VL) method of the embedded service on basis of the coverage matrix [6,7]; 3) VL-method application for the diagnosis of SoC components; 4) Practical results of the investigations. Modern technologies for the design of digital systems on chip [8-11] offer, along with the functional blocks of F-IP, the development of service modules IIP oriented on the integrated solution of the problem of improving the project quality and Yield increasing in the manufacturing process, which is defined by implementation to silicon the following services [2,4,5]: 1) Monitoring the internal and output lines in the operation, verification and testing of functional blocks on the basis of IEEE 1500 boundary scan standard [12]; 2) Testing the functional modules by applying different test generators, targeting fault detection or behaviour checking; 3) Diagnosis failures and defects by analyzing the information received from testing phase and by using the special embedded methods for troubleshooting based on the IEEE 1500 standard [12]; 4) Repair of functional modules and memory after fixing a negative test result and determination the type and location of a defect at the executing diagnosis phase; 5) Built-in-measurement the main parameters and characteristics of SoC operation, allowing the temporal and volt-ampere measurements; 6) The reliability and fault tolerance of SoC in the operation, which are achieved by using diversification of functional blocks, duplication of them and recovery SoC efficiency in real time. Subject to the SoC testing problem’s state the fault diagnosis problem is considered below, defined by item 3; its solving enables to raise the quality of designed device essentially due to technological method of a single and multiple faults detection.
URI: http://openarchive.nure.ua/handle/document/2132
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

Files in This Item:
File Description SizeFormat 
Хаханов_EWDTS_2008.pdf1.17 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.