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|Title:||Testing Challenges of SOC Hardware-Software Components|
|Citation:||Hahanov Vladimir Testing Challenges of SOC Hardware-Software Components /Vladimir Hahanov, Volodimir Obrizan, Sergey Miroshnichenko, Alexander Gorobets //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)|
|Abstract:||Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. Adaptation of testing and verification methods of digital systems can bring in big financial and time dividends, when using for testable design and diagnosis of software. Consideration of the following questions can be interesting: 1. Classification of key uses of SoC testable design technologies in software testing and verification problems. 2. Universal model of hardware and software component in the form of directed register transfer and control graph, on which the testable design, test synthesis and analysis problems can be solved. 3. Metrics of testability (controllability and observability) evaluation for hardware and software by the graph register transfer and control model. The silicon chip that is basis of computers and communicators development has to be considered as the initiate kernel of new testing and verification technologies appearance in software and computer engineering. A chip is used as test area for new facilities and methods creation and testing for component routing, placement, synthesis and analysis. Technological solutions, tested by time in microelectronics, then are captured and implemented into macroelectronics (computer systems and networks). Here are some of artifacts, relating to the continuity of technological innovations development|
|Appears in Collections:||Кафедра автоматизації проектування обчислювальної техніки (АПОТ)|
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